Abstract: In one example, a micro device includes a housing; a chip package disposed in the housing; a noise producing component coupled to the housing. The micro device also includes a noise reduction system having a reference microphone for detecting a noise from the noise producing component and a controller configured to receive the noise from the reference microphone and generate a masking sound signal in response to the detected noise. A speaker is coupled to the housing for producing a masking sound corresponding to the masking sound signal, whereby the masking sound reduces the noise. In another example, the noise producing component comprises a fan.

Abstract: A chip package includes a substrate and an integrated circuit (“IC”) die mounted to the substrate. A stiffener frame is mounted to the substrate and circumscribes the IC die. The stiffener frame has a plurality of connected walls that define an opening in the stiffener frame. The chip package also includes a lid having a bottom side facing a top surface of the IC die. The lid has at least a first guide and a second guide extending from the bottom side of the lid. The first guide can be disposed outward or inward of the stiffener frame. The first guide has a side facing an outer wall surface or an inner wall surface of the stiffener frame. The first guide and the second guide are positioned to limit movement of the lid relative to the stiffener frame in two directions.

Abstract: An apparatus for component cooling includes a thermoelectric cooling (TEC) device configured to be thermally coupled to a first processor, and a controller. The controller is configured to receive at least one first parameter indicative of a first activity level of the first processor; determine a TEC power level from among a plurality of TEC power levels based on the at least one first parameter; and control providing of power to the TEC device at the determined TEC power level.

Abstract: An apparatus for component cooling includes a first heat transfer element configured to be thermally coupled to a heat-generating electronic component, and a second heat transfer element. The apparatus further includes a plurality of heat transfer paths thermally coupled between the first heat transfer element and the second heat transfer element. Each of the plurality of heat transfer paths configured to provide a separate heat conduction path from the first heat transfer element to the second heat transfer element. The apparatus further includes a manifold including a first fluid passage providing a first portion of a heat transfer fluid in thermal contact with the first heat transfer element, and a second fluid passage providing a second portion of the heat transfer fluid in thermal contact with the second heat transfer element.

Abstract: An integrated coprocessor such as an accelerated processing unit (APU) generates commands for execution on a discrete coprocessor such as a discrete graphics processing unit (dGPU). Power distribution circuitry selectively provides power to the APU and the dGPU based on characteristics of workloads executing on the APU and the dGPU and based on a platform power limit that is shared by the APU and the dGPU. In some cases, the power distribution circuitry determines a first power provided to the APU and a second power provided to the dGPU. The power distribution circuitry increases the second power provided to the dGPU in response to a sum of the first and second powers being less than the platform power limit. In some cases, the power distribution circuitry modifies the power provided to the APU, the dGPU, or both in response to changes in temperatures measured by a set of sensors.

Abstract: Various methods an apparatus to use facial recognition in a computing device are disclosed. In one aspect, a method of controlling a component of a computing device is provided. The method includes taking an IR image of a user and a background with an IR sensor of a computing device. The computing device is in a location. The IR image is segmented into user image data and background image data. An ambient temperature of the location is determined using the background image data. An aspect of the component is controlled based on the ambient temperature.

Abstract: A processing unit manages temperature by correlating readings from a plurality of external temperature sensors to a skin temperature of the processing unit, wherein the correlation is based on characteristics of a computer chassis that is to include the processing unit. The processing unit is mounted on a printed circuit board (PCB) or other substrate that is to be placed in a computer chassis. Each of a plurality of temperature sensors is placed at a different location of the PCB to provide temperature readings from a variety of locations of the PCB. A temperature controller of the processing unit receives temperature readings from the plurality of sensors and correlates the temperature readings with a skin temperature of the processing unit based on a plurality of correlation values.

Abstract: An integrated coprocessor such as an accelerated processing unit (APU) generates commands for execution on a discrete coprocessor such as a discrete graphics processing unit (dGPU). Power distribution circuitry selectively provides power to the APU and the dGPU based on characteristics of workloads executing on the APU and the dGPU and based on a platform power limit that is shared by the APU and the dGPU. In some cases, the power distribution circuitry determines a first power provided to the APU and a second power provided to the dGPU. The power distribution circuitry increases the second power provided to the dGPU in response to a sum of the first and second powers being less than the platform power limit. In some cases, the power distribution circuitry modifies the power provided to the APU, the dGPU, or both in response to changes in temperatures measured by a set of sensors.

Abstract: Various thermal management devices for providing thermal management of integrated circuit chips are disclosed. In one aspect, a thermal management device is provided that has a heat spreader plate that includes mechanical connection structures to enable the heat spreader plate to mount on a first circuit board and thermally contact the integrated circuit chip when the integrated circuit chip is directly mounted on the first circuit board and to enable the heat spreader plate to mount on a second circuit board having a socket and thermally contact the integrated circuit chip when the integrated circuit chip is mounted in the socket.

Abstract: Various methods an apparatus to use facial recognition in a computing device are disclosed. In one aspect, a method of controlling a component of a computing device is provided. The method includes taking an IR image of a user and a background with an IR sensor of a computing device. The computing device is in a location. The IR image is segmented into user image data and background image data. An ambient temperature of the location is determined using the background image data. An aspect of the component is controlled based on the ambient temperature.

Abstract: Various thermal management devices for providing thermal management of integrated circuit chips are disclosed. In one aspect, a thermal management device is provided that has a heat spreader plate that includes mechanical connection structures to enable the heat spreader plate to mount on a first circuit board and thermally contact the integrated circuit chip when the integrated circuit chip is directly mounted on the first circuit board and to enable the heat spreader plate to mount on a second circuit board having a socket and thermally contact the integrated circuit chip when the integrated circuit chip is mounted in the socket.

Abstract: A heat exchanger with mini channels or micro channels provides enhanced heat transfer abilities. One or more surfaces of the channels may be covered with a nanostructure, such as single walled carbon nanotubes or multiwalled carbon nanotubes. The nanostructures may fully cover the entire surface of the channel or a selected surface area of the channel. Further, the nanostructures may be arranged into multiple patterned bundles covering the surface of the channel.