Abstract: A system, a method, and a machine-readable medium for overclocking a computer system is provided. An example of a method for overclocking a computer system includes predicting a stable operating frequency for a central processing unit (CPU) in a target system based, at least in part, on a model generated from data collected for a test system. An operating frequency for the CPU is adjusted to the stable operating frequency. A benchmark test is run to confirm that the CPU is operating within limits.

Abstract: A method of automatic overclocking of a silicon part or chip, such as a central processing unit (CPU) is disclosed. A range of clock frequencies of both the CPU and a cache of a computer system are tested, with parameters being monitored, safety limits of the computer system being ensured, and benchmark tests being run, before arriving at a CPU and cache frequencies based on a selected benchmark score.

Abstract: A method is described in which electronic circuitry of a mobile device is powered by a plurality of battery cells that are selectably connectable in series and in parallel. The energy utilization of the circuitry is measured during operation. The power efficiency for series and parallel configurations of the battery cells is determined based on the measured energy utilization. The battery cells are configured in series or in parallel based on which of the series and parallel configurations is determined to provide a higher efficiency of energy utilization during operation.

Abstract: A system, a method, and a machine-readable medium for overclocking a computer system is provided. An example of a method for overclocking a computer system includes predicting a stable operating frequency for a central processing unit (CPU) in a target system based, at least in part, on a model generated from data collected for a test system. An operating frequency for the CPU is adjusted to the stable operating frequency. A benchmark test is run to confirm that the CPU is operating within limits.

Abstract: A method of automatic overclocking of a silicon part or chip, such as a central processing unit (CPU) is disclosed. A range of clock frequencies of both the CPU and a cache of a computer system are tested, with parameters being monitored, safety limits of the computer system being ensured, and benchmark tests being run, before arriving at a CPU and cache frequencies based on a selected benchmark score.

Abstract: A method, according to one example, includes sensing audio information with an audio microphone of a computing device. The method includes determining, by a controller of the computing device, whether the sensed audio information indicates footsteps moving toward the computing device. The method includes causing, by the controller, a powering up of a presence sensor having a higher power consumption than the microphone in response to a determination by the controller that the sensed audio information indicates footsteps moving toward the computing device.

Abstract: A method is described in which electronic circuitry of a mobile device is powered by a plurality of battery cells that are selectably connectable in series and in parallel. The energy utilization of the circuitry is measured during operation. The power efficiency for series and parallel configurations of the battery cells is determined based on the measured energy utilization. The battery cells are configured in series or in parallel based on which of the series and parallel configurations is determined to provide a higher efficiency of energy utilization during operation.

Abstract: According to some embodiments, a first filter receives input pixel information and provides a first output. A buffer stores the first output, and a second filter receives information from the buffer and provides output pixel information. Moreover, at least one of the first or second filters are configurable to support motion compensation for a plurality of video compression standards.

Abstract: Embodiments relate to converting or compressing symbols or run, level pair of an input digital video or image data stream to variable length code (VLC) by looking the symbols or run, level pairs up in a table including a binary code, a length code, and a flip code and constructing the VLC therefrom. For instance, the binary code may identify a first non-zero portion of the VLC, the length may identify the length of the VLC, and the flip code may identify whether or not the first portion and a number of 0's appended to the first portion to form a VLC having the length given by the length code, must be inverted to create the VLC. Also, the table may include entries grouped according to symbol or run, level pair values, and an address offset determined by the symbol or run, level pair or the input may be used to access the binary, length, and flip code from the appropriate group.

Abstract: A device including a variable length coding unit that includes an input unit connected to a stream switching unit, and an output unit connected to the stream switching unit. The input unit to encode at least two input streams simultaneously. The output unit to transmit output streams to an output interface connected to the output unit.