Patents by Inventor Suketu U. Bhatt
Suketu U. Bhatt has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 10705142Abstract: Techniques and mechanisms for providing on-chip link control functionality to facilitate emulation of a communication. In an embodiment, an integrated circuit (IC) chip includes a physical layer (PHY) which supports communication compatible with a high-speed serial interface standard. A link controller of the IC chip is coupled between the PHY and an interconnect architecture which variously couples a host and other resources of the IC chip to each other. A test controller of the IC chip signals a test mode to implement a loopback path of the link controller in lieu of one or more functional paths for communication with the PHY. In another embodiment, signal output by the loopback path emulate a communication from a resource other than the test controller.Type: GrantFiled: December 29, 2016Date of Patent: July 7, 2020Assignee: INTEL CORPORATIONInventors: Lakshminarayana Pappu, Suketu U. Bhatt, Satheesh Chellappan
-
Patent number: 10664433Abstract: In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing SoC coverage through virtual devices in PCIe and DMI controllers.Type: GrantFiled: June 30, 2016Date of Patent: May 26, 2020Assignee: Intel CorporationInventors: Lakshminarayana Pappu, Timothy J. Callahan, Hem Doshi, Hooi Kar Loo, Suketu U. Bhatt
-
Patent number: 10657092Abstract: In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing high speed serial controller testing.Type: GrantFiled: June 30, 2016Date of Patent: May 19, 2020Assignee: Intel CorporationInventors: Lakshminarayana Pappu, Timothy J. Callahan, Hem Doshi, Hooi Kar Loo, Suketu U. Bhatt
-
Patent number: 10484361Abstract: In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing virtual device observation and debug network for high speed serial IOS.Type: GrantFiled: June 30, 2016Date of Patent: November 19, 2019Assignee: Intel CorporationInventors: Lakshminarayana Pappu, Timothy J. Callahan, Baruch Schnarch, Hem Doshi, Suketu U. Bhatt
-
Patent number: 10127162Abstract: Described is a host interface, a device interface, a downstream translation circuitry, an upstream translation circuitry, and a host line-state state machine. The host interface may comprise a host line-state output. The device interface may comprise a device line-state output. The downstream translation circuitry may be operable to process a transaction received on the host interface and to generate a transaction for the device interface. The upstream translation circuitry may be operable to process a transaction received on the device interface and to generate a transaction for the host interface. The host line-state state machine may be operable to set the host line-state output to a value that is one of: an SE0-state value, a J-state value, or a K-state value.Type: GrantFiled: June 29, 2016Date of Patent: November 13, 2018Assignee: Intel CorporationInventors: Suketu U. Bhatt, Lakshminarayana Pappu, Satheesh Chellappan
-
Patent number: 10042729Abstract: An apparatus and method are described for a scalable testing agent. For example, one embodiment of a scalable test engine comprises: an input interface to receive commands and/or data from a processor core or an external test system, the commands and/or data to specify one or more test operations to be performed on one or more intellectual property (IP) blocks of a chip; a first circuit to establish communication with an IP block over an interconnect fabric, the first circuit to transmit the one or more test operations to the IP block responsive to the received commands and/or data, the IP block to process the test operations and generate results; and a second circuit to receive the results from the IP block over the interconnect fabric, the results to be provided from the second circuit to the processor core and/or the external test system for analysis.Type: GrantFiled: April 1, 2016Date of Patent: August 7, 2018Assignee: Intel CorporationInventors: Lakshminarayana Pappu, Robert De Gruijl, Suketu U. Bhatt, Robert P. Adler, R Selvakumar Raja Gopal, Rius Tanadi
-
Publication number: 20180188321Abstract: Techniques and mechanisms for providing on-chip link control functionality to facilitate emulation of a communication. In an embodiment, an integrated circuit (IC) chip includes a physical layer (PHY) which supports communication compatible with a high-speed serial interface standard. A link controller of the IC chip is coupled between the PHY and an interconnect architecture which variously couples a host and other resources of the IC chip to each other. A test controller of the IC chip signals a test mode to implement a loopback path of the link controller in lieu of one or more functional paths for communication with the PHY. In another embodiment, signal output by the loopback path emulate a communication from a resource other than the test controller.Type: ApplicationFiled: December 29, 2016Publication date: July 5, 2018Inventors: Lakshminarayana Pappu, Suketu U. Bhatt, Satheesh Chellappan
-
Patent number: 9971644Abstract: One embodiment provides an apparatus. The apparatus includes a functional test controller. The functional test controller includes controller logic to receive communication protocol-specific data comprising a packet header from a tester; a protocol buffer to store the packet header; and a pseudorandom bit sequence (PRBS) generator to generate a PRBS. The controller logic is to combine the packet header and the PRBS into a packet and to provide the packet to an input/output (I/O) controller under test.Type: GrantFiled: December 24, 2015Date of Patent: May 15, 2018Assignee: Intel CorporationInventors: Suketu U. Bhatt, Yuen Tat Lee, Lakshminarayana Pappu
-
Patent number: 9891282Abstract: Described is a signature accumulator with a first set of logic devices, a second set of logic devices, and a memory device. The first set of logic devices includes compaction logic that couples an N-bit input bus to a K-bit first intermediate bus. The second set of logic devices includes commutative arithmetic operation logic that couples both the K-bit first intermediate bus and a K-bit signature bus to a K-bit second intermediate bus. The memory storage device includes a storage element that couples the K-bit second intermediate bus to the K-bit signature bus. The K-bit signature bus is also coupled to a valid-data input signal path.Type: GrantFiled: December 24, 2015Date of Patent: February 13, 2018Assignee: Intel CorporationInventors: Lakshminarayana Pappu, Robert P. Adler, Suketu U. Bhatt, Robert De Gruijl, Kah Meng Yeem
-
Publication number: 20180007032Abstract: In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing virtual device observation and debug network for high speed serial IOS.Type: ApplicationFiled: June 30, 2016Publication date: January 4, 2018Inventors: LAKSHMINARAYANA PAPPU, TIMOTHY J. CALLAHAN, BARUCH SCHNARCH, HEM DOSHI, SUKETU U. BHATT
-
Publication number: 20180004685Abstract: Described is a host interface, a device interface, a downstream translation circuitry, an upstream translation circuitry, and a host line-state state machine. The host interface may comprise a host line-state output. The device interface may comprise a device line-state output. The downstream translation circuitry may be operable to process a transaction received on the host interface and to generate a transaction for the device interface. The upstream translation circuitry may be operable to process a transaction received on the device interface and to generate a transaction for the host interface. The host line-state state machine may be operable to set the host line-state output to a value that is one of: an SE0-state value, a J-state value, or a K-state value.Type: ApplicationFiled: June 29, 2016Publication date: January 4, 2018Inventors: Suketu U. Bhatt, Lakshminarayana Pappu, Satheesh Chellappan
-
Publication number: 20180004701Abstract: In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing high speed serial controller testing.Type: ApplicationFiled: June 30, 2016Publication date: January 4, 2018Inventors: LAKSHMINARAYANA PAPPU, TIMOTHY J. CALLAHAN, HEM DOSHI, HOOI KAR LOO, SUKETU U. BHATT
-
Publication number: 20180004702Abstract: In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing SoC coverage through virtual devices in PCIe and DMI controllers.Type: ApplicationFiled: June 30, 2016Publication date: January 4, 2018Inventors: LAKSHMINARAYANA PAPPU, TIMOTHY J. CALLAHAN, HEM DOSHI, HOOI KAR LOO, SUKETU U. BHATT
-
Publication number: 20170286247Abstract: An apparatus and method are described for a scalable testing agent. For example, one embodiment of a scalable test engine comprises: an input interface to receive commands and/or data from a processor core or an external test system, the commands and/or data to specify one or more test operations to be performed on one or more intellectual property (IP) blocks of a chip; a first circuit to establish communication with an IP block over an interconnect fabric, the first circuit to transmit the one or more test operations to the IP block responsive to the received commands and/or data, the IP block to process the test operations and generate results; and a second circuit to receive the results from the IP block over the interconnect fabric, the results to be provided from the second circuit to the processor core and/or the external test system for analysis.Type: ApplicationFiled: April 1, 2016Publication date: October 5, 2017Inventors: LAKSHMINARAYANA PAPPU, ROBERT DE GRUIJL, SUKETU U. BHATT, ROBERT P. ADLER, R SELVAKUMAR RAJA GOPAL, RIUS TANADI
-
Publication number: 20170184667Abstract: One embodiment provides an apparatus. The apparatus includes a functional test controller. The functional test controller includes controller logic to receive communication protocol-specific data comprising a packet header from a tester; a protocol buffer to store the packet header; and a pseudorandom bit sequence (PRBS) generator to generate a PRBS. The controller logic is to combine the packet header and the PRBS into a packet and to provide the packet to an input/output (I/O) controller under test.Type: ApplicationFiled: December 24, 2015Publication date: June 29, 2017Applicant: Intel CorporationInventors: Suketu U. Bhatt, Yuen Tat Lee, Lakshminarayana Pappu
-
Publication number: 20170184666Abstract: Described is a signature accumulator with a first set of logic devices, a second set of logic devices, and a memory device. The first set of logic devices includes compaction logic that couples an N-bit input bus to a K-bit first intermediate bus. The second set of logic devices includes commutative arithmetic operation logic that couples both the K-bit first intermediate bus and a K-bit signature bus to a K-bit second intermediate bus. The memory storage device includes a storage element that couples the K-bit second intermediate bus to the K-bit signature bus. The K-bit signature bus is also coupled to a valid-data input signal path.Type: ApplicationFiled: December 24, 2015Publication date: June 29, 2017Inventors: Lakshminarayana Pappu, Robert P. Adler, Suketu U. Bhatt, Robert De Gruijl, Kah Meng Yeem