Patents by Inventor Sukhbinder Singh

Sukhbinder Singh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20260186745
    Abstract: Random number generation is crucial in applications such as cryptography, simulations, and statistical sampling. However, traditional methods often rely on algorithmic processes, which may not provide true randomness. An example solution may provide a computer-implemented method including: receiving a data set, a processing time, and a state count; executing one or more simulations of a quantum adiabatic process based on the data set, the processing time, the state count, an energy function, and one or more network structures, the one or more network structures including a representation of one or more initial simulated quantum bits; measuring one or more simulated values based on the one or more evolved simulated quantum bits at the end of each simulation; and outputting one or more output values based on the one or more simulated values, the one or more output values including one or more classical bit.
    Type: Application
    Filed: September 15, 2025
    Publication date: July 2, 2026
    Inventors: Borja Aizpurua, Sukhbinder Singh, Roman Orus
  • Publication number: 20260187492
    Abstract: Various methods and systems for determining a decision for an offline hardware system that includes at least one system processor, sensors and at least one specialized hardware processor are described herein. The method involves receiving, at the at least one system processor, sensor data from the sensors, preprocessing, at the at least one system processor, the sensor data to obtain preprocessed sensor data; determining, at the at least one specialized hardware processor, using one or more trained decision-making models the decision for the offline hardware system based on the preprocessed sensor data and generating a command for the hardware system based on the decision. Each of the one or more decision-making models is a large language model (LLM) compressed using tensor networks. The offline hardware system can be a component of systems or devices.
    Type: Application
    Filed: August 1, 2025
    Publication date: July 2, 2026
    Inventors: Román Orús, Saeed Jahromi, Sukhbinder Singh
  • Publication number: 20260189364
    Abstract: A computer-implemented method for recovering a plaintext is disclosed. The plaintext (300) comprises a variable string (320). The method comprises constructing (S2) a tensor network (500) representing the variable string (320), optimizing (270) the tensor network (500), generating (S3), in a hash function generator (350), a candidate hash (370) based on the output of the tensor network (330), determining (S4) an overlap (390) between the candidate hash (370) and a reference ciphertext (380); and on reaching a zero-overlap value, determining the variable string (320), otherwise optimising the tensor network (500).
    Type: Application
    Filed: July 29, 2025
    Publication date: July 2, 2026
    Inventors: Roman Orus, Borja Aizpurua, Sukhbinder Singh, Saeed Jahromi
  • Publication number: 20260189374
    Abstract: The present invention proposes a computer implemented method and system for determining a cryptographic key. The method comprises constructing a tensor network with parameters representing a candidate cryptographic key; adjusting the parameters of the tensor network; generating a candidate key sample and obtaining a candidate ciphertext obtained with the candidate cryptographic key; calculating a cost function with respect to a target ciphertext, measuring an overlap between the target ciphertext and the candidate ciphertext, determining whether the overlap has reached a threshold value. If threshold value is not reached, repeating the method by further adjusting the parameters of the tensor network, if the threshold value is reached, determining that the candidate cryptographic key is the cryptographic key.
    Type: Application
    Filed: July 29, 2025
    Publication date: July 2, 2026
    Inventors: Roman Orus, Borja Aizpurua, Sukhbinder Singh, Saeed Jahromi
  • Publication number: 20260178951
    Abstract: The disclosure relates to a quantum computing system comprising: a reservoir of quantum computational units, wherein the quantum computational units are disposed in a non-lattice computational arrangement; means for computationally manipulating quantum computational units of the reservoir; means for enabling computational interaction between at least two quantum computational units computationally manipulated; and a measurement means for measuring a quantum property of at least one of the at least two quantum computational units after said computational interaction.
    Type: Application
    Filed: December 27, 2024
    Publication date: June 25, 2026
    Inventors: Siddhartha PATRA, Sukhbinder SINGH, Saeed JAHROMI, Román ORÚS
  • Publication number: 20260154557
    Abstract: The method enhances computational efficiency and performance of large language models (LLMs) through hybrid classical-quantum processing. The method involves a classical computer receiving an input for processing by a selected LLM comprising deep self-attention and multilayer perceptron layers and decomposing the LLM's weight matrices into a first Matrix Product Operator (MPO). The classical computer identifies one or more disentanglers which factorize the MPO into a non-unitary tensor network and a set of unitary subcomponents. The non-unitary tensor network enables compression by localizing quantum correlations. The unitary subcomponents correspond to first and second variational quantum circuits, configured to run sequentially on a quantum computer. The execution of the second quantum circuit is conditioned on both the measurements of the first quantum circuit and outputs from the tensor network, enabling enhanced correlation capture and efficient model representation.
    Type: Application
    Filed: September 4, 2025
    Publication date: June 4, 2026
    Inventors: Borja AIZPURUA, Sukhbinder SINGH, Saeed S. JAHROMI, Roman ORUS
  • Publication number: 20260111512
    Abstract: A computer implemented method for solving a classical optimization problem of integer factorization implemented on a digital computer system is described. The method is implemented on a classical processor adapted to execute a time evolving block decimation algorithm. The method comprises in a first step an inputting a lattice basis and a target lattice vector to an input device of the classical processor followed by an implementing a lattice basis reduction algorithm on the lattice basis in an implementation module, thereby obtaining a reduced orthogonal lattice basis. The method further comprises a projecting the target lattice vector on the reduced orthogonal lattice basis followed by a building a closest vector to the target lattice vector and optimizing the closest vector using a tropical time-evolving block decimation algorithm by the classical processor and finally outputting an integer vector.
    Type: Application
    Filed: September 30, 2024
    Publication date: April 23, 2026
    Inventors: Sukhbinder SINGH, Roman ORUS
  • Publication number: 20260111743
    Abstract: A computer-implemented method for improving the computational efficiency and performance of large language models (LLMs) within at least one hybrid classical-quantum computation system with involving quantum circuits and tensor networks; and the classical computing device applies disentanglers to decompose the weight matrices of self-attention layers and multilayer perceptron (MLP) layers of a pre-selected large language model (LLM) into an unitary quantum circuits and a non-unitary tensor network for allowing transformation into quantum circuits into quantum gates; and sends this information to at least one quantum computing device within a quantum circuits; and processes non-unitary tensor network with at least one classical computing device and combines both results to reconstruct the large language model; and enlarges the bond dimension of the non-unitary tensor network and the number of layers of the quantum circuits; and optimizes the new parameters variationally in order to improve the accuracy beyond
    Type: Application
    Filed: November 12, 2024
    Publication date: April 23, 2026
    Inventors: Borja AIZPURUA, Saeed S. JAHROMI, Sukhbinder SINGH, Roman OROS
  • Publication number: 20260105343
    Abstract: A method for modifying a quantum neural network includes the steps of: identifying via a computer information that needs to be erased from a trained quantum neural network; localizing via the computer the identified information in the trained quantum neural network; erasing via the computer the identified information from the trained quantum neural network without erasing from the trained quantum neural network other information that needs not to be erased; and compressing via the computer the quantum neural network which results when the identified information has been erased. A system including similar components is related.
    Type: Application
    Filed: October 18, 2024
    Publication date: April 16, 2026
    Inventors: Roman ORUS, Saeed JAHROMI, Sukhbinder SINGH, Andrei TOMUT
  • Publication number: 20260093768
    Abstract: A system configured for: breaking down a cost function into two-bit terms; applying a two-bit gate of temporal evolution and step change to a selected two-bit term, thereby generating a tensor per bit, with a connecting tensor index between the two tensors; shortening the connecting tensor index; removing at least as many connecting tensors as needed to reduce the number of connecting tensor indices down to a threshold M; and applying, shortening and removing for one, some or all other two-bit terms of the cost function at least until a solution to the cost function reaches a predetermined convergence.
    Type: Application
    Filed: November 21, 2024
    Publication date: April 2, 2026
    Inventors: Siddhartha PATRA, Sukhbinder SINGH, Saeed JAHROMI, Roman ORUS
  • Publication number: 20260094045
    Abstract: Simulating a quantum computer by generating a dynamic tensor network according to a structure of a quantum circuit to be simulated. Reading two-qubit terms of the quantum circuit; providing a two-qubit gate for each read two-qubit term thereby providing a tensor per qubit, and a connecting tensor index for the two tensors; shortening the connecting tensor index by using a value decomposition and keeping a predetermined number D of largest values; removing at least as many connecting tensor indices as needed to reduce the number of connecting tensor indices down to a predetermined threshold M if the number exceeds M.
    Type: Application
    Filed: November 21, 2024
    Publication date: April 2, 2026
    Inventors: Siddhartha PATRA, Sukhbinder SINGH, Saeed JAHROMI, Roman ORUS
  • Publication number: 20250209367
    Abstract: A computer-implemented method and system for simulating quantum computations using a lattice-free tensor network simulation that adapts dynamically to an interaction pattern in the quantum computation. The method includes initializing an initial state, applying a quantum gate on two quantum bits, generating a connection in a network structure, truncating numerical values using a mathematical decomposition and an update process, computing an entropy measure for all connections, truncating the connections with the lowest entropy measure to a dimensional parameter, and computing expectation values of observables at the end of the simulation. The system includes modules and submodules for performing these steps.
    Type: Application
    Filed: December 28, 2023
    Publication date: June 26, 2025
    Inventors: Roman ORÚS, Saeed JAHROMI, Sukhbinder SINGH, Siddhartha PATRA
  • Publication number: 20250209374
    Abstract: A computational framework and a method for implementing symmetric tensor networks for quantum machine learning using symmetric deep learning involve the execution of techniques to deploy a computational framework, creation of mathematical structures for machine learning, and utilization of deep learning for faster convergence and training. The system includes hardware components to implement the model, an optimization technique to adjust elements, and an inference module for predictions over new datapoints. The mathematical structures used are symmetric tensor networks, which are built using the symmetries of the dataset and replace the weight matrices in the deep learning module.
    Type: Application
    Filed: December 28, 2023
    Publication date: June 26, 2025
    Inventors: Roman ORÚS, Saeed JAHROMI, Sukhbinder SINGH
  • Publication number: 20250111004
    Abstract: A computer implemented method for solving a classical optimization problem of integer factorization implemented on a digital computer system is described. The method is implemented on a classical processor adapted to execute a time evolving block decimation algorithm. The method comprises in a first step an inputting a lattice basis and a target lattice vector to an input device of the classical processor followed by an implementing a lattice basis reduction algorithm on the lattice basis in an implementation module, thereby obtaining a reduced orthogonal lattice basis. The method further comprises a projecting the target lattice vector on the reduced orthogonal lattice basis followed by a building a closest vector to the target lattice vector and optimizing the closest vector using a tropical time-evolving block decimation algorithm by the classical processor and finally outputting an integer vector.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 3, 2025
    Inventors: Sukhbinder SINGH, Roman ORUS
  • Publication number: 20070171833
    Abstract: A method to be executed within a computing system having a network that couples a processor to a memory controller is described. The method involves receiving a packet and then characterizing the packet as being of a type selected from the group consisting of: i) a debug packet; ii) a system maintenance packet; and, iii) a packet having a destination identifier or connection identifier for which a primary routing table has no entry. The method also involves, because the packet is of the type, using a secondary routing table to identify at least one output port upon which the packet is to be transmitted.
    Type: Application
    Filed: November 21, 2005
    Publication date: July 26, 2007
    Inventors: Sukhbinder Singh, Anil Jonnalagadda, Uday Joshi, Tessil Thomas