Patents by Inventor Sukhbir Singh Dulay

Sukhbir Singh Dulay has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7454828
    Abstract: A method for measuring recession in a wafer undergoing an asymmetrical ion mill process. The method includes the formation of first and second reference features and possibly a dummy feature. The reference features are constructed such that the location of the midpoint between them is unaffected by the asymmetrical ion mill. By measuring the distance between a portion of the dummy feature and the midpoint between the reference features, the amount of recession of the dummy feature can be measured. The measurement can be used to calculate the relative location of the flare to the read sensor rear edge through overlay information. By keeping the angles of the sides of the features steep (ie. nearly parallel with the direction in which the ion mill is asymmetrical) the amount of material consumed on each of the reference features is substantially equal and the midpoint between the reference features is substantially stationary.
    Type: Grant
    Filed: November 23, 2005
    Date of Patent: November 25, 2008
    Assignee: Hitachi Global Storage Technologies Netherlands B.V.
    Inventors: Sukhbir Singh Dulay, Justin Jia-Jen Hwu, Thao John Pham
  • Patent number: 7323350
    Abstract: A method of making and using thin film calibration features is described. To fabricate a calibration standard according to the invention raised features are first formed from an electrically conductive material with a selected atomic number. A conformal thin film layer is deposited over the exposed sidewalls of the raised features. The sidewall material is selected to have a different atomic number and is preferably an nonconductive such as silicon dioxide or alumina. After the nonconductive material deposition, a controlled directional RIE process is used to remove the insulator layer deposited on the top and bottom surface of the lines and trenches. The remaining voids between the sidewalls of the raised features are filled with a conductive material. The wafer is then planarized with chemical mechanical planarization (CMP) to expose the nonconductive sidewall material on the surface. The nonconductive sidewall material will be fine lines embedded in conductive material.
    Type: Grant
    Filed: September 30, 2004
    Date of Patent: January 29, 2008
    Assignee: Hitachi Global Storage Technologies Netherlands B.V.
    Inventors: Sukhbir Singh Dulay, Justin Jia-Jen Hwu, Thao John Pham
  • Patent number: 7186574
    Abstract: A method for forming metrology structures for a CMP process is described. A trench edge is formed in a base material or stack of materials which are preferably deposited as part of the process of fabricating the production structures on the wafer. A covering film of a second material with preferably with contrasting SEM properties is deposited over the trench edge in the base material. During CMP the covering film is preferentially worn away at the edge revealing the base material. The width of the base material which has been revealed is a measure of the progress of the CMP. Since the base material and the covering material are preferably selected to have contrasting images in an SEM, a CD-SEM can be used to precisely measure the CMP progress.
    Type: Grant
    Filed: September 30, 2004
    Date of Patent: March 6, 2007
    Assignee: Hitachi Global Storage Technologies Netherlands B.V.
    Inventors: Sukhbir Singh Dulay, Thomas L. Leong, John Jaekoyun Yang