Patents by Inventor Suk-jin Chung

Suk-jin Chung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10526706
    Abstract: A gas supply unit includes a base plate, a plurality of gas supply regions protruding from the base plate and arranged on the base plate in a circumferential direction, and a plurality of sidewall trenches alternating with the gas supply regions on the base plate. A distance between opposing surfaces of the base plate increases in a radial direction from a center of the base plate in each of the plurality of sidewall trenches, so each of the plurality of sidewall trenches has a depth that decreases in the radial direction from the center of the base plate.
    Type: Grant
    Filed: April 12, 2017
    Date of Patent: January 7, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Suk Jin Chung, Jong Cheol Lee, Jae chul Shin, Min Hwa Jung, Jin Pil Heo
  • Publication number: 20180002808
    Abstract: A gas supply unit includes a base plate, a plurality of gas supply regions protruding from the base plate, the plurality of gas supply regions being arranged on the base plate in a circumferential direction, and a plurality of sidewall trenches defined by facing sidewalls of adjacent gas supply regions of the plurality of gas supply regions, wherein each of the plurality of sidewall trenches has a depth that decreases in a radial direction from a center of the base plate.
    Type: Application
    Filed: April 12, 2017
    Publication date: January 4, 2018
    Inventors: Suk Jin CHUNG, Jong Cheol LEE, Jae chul SHIN, Min Hwa JUNG, Jin Pil HEO
  • Patent number: 9685498
    Abstract: To form a dielectric layer, an organometallic precursor is adsorbed on a substrate loaded into a process chamber. The organometallic precursor includes a central metal and ligands bound to the central metal. An inactive oxidant is provided onto the substrate. The inactive oxidant is reactive with the organometallic precursor. An active oxidant is also provided onto the substrate. The active oxidant has a higher reactivity than that of the inactive oxidant.
    Type: Grant
    Filed: July 5, 2016
    Date of Patent: June 20, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Yeol Kang, Suk-Jin Chung, Youn-Soo Kim, Jae-Hyoung Choi, Jae-Soon Lim, Min-Young Park
  • Publication number: 20160315137
    Abstract: To form a dielectric layer, an organometallic precursor is adsorbed on a substrate loaded into a process chamber. The organometallic precursor includes a central metal and ligands bound to the central metal. An inactive oxidant is provided onto the substrate. The inactive oxidant is reactive with the organometallic precursor. An active oxidant is also provided onto the substrate. The active oxidant has a higher reactivity than that of the inactive oxidant.
    Type: Application
    Filed: July 5, 2016
    Publication date: October 27, 2016
    Inventors: SANG-YEOL KANG, SUK-JIN CHUNG, YOUN-SOO KIM, JAE-HYOUNG CHOI, JAE-SOON LIM, MIN-YOUNG PARK
  • Patent number: 9412583
    Abstract: To form a dielectric layer, an organometallic precursor is adsorbed on a substrate loaded into a process chamber. The organometallic precursor includes a central metal and ligands bound to the central metal. An inactive oxidant is provided onto the substrate. The inactive oxidant is reactive with the organometallic precursor. An active oxidant is also provided onto the substrate. The active oxidant has a higher reactivity than that of the inactive oxidant.
    Type: Grant
    Filed: February 21, 2012
    Date of Patent: August 9, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Yeol Kang, Suk-Jin Chung, Youn-Soo Kim, Jae-Hyoung Choi, Jae-Soon Lim, Min-Young Park
  • Patent number: 9076647
    Abstract: A method of forming an oxide layer. The method includes: forming a layer of reaction-inhibiting functional groups on a surface of a substrate; forming a layer of precursors of a metal or a semiconductor on the layer of the reaction-inhibiting functional groups; and oxidizing the precursors of the metal or the semiconductor in order to obtain a layer of a metal oxide or a semiconductor oxide. According to the method, an oxide layer having a high thickness uniformity may be formed and a semiconductor device having excellent electrical characteristics may be manufactured.
    Type: Grant
    Filed: April 28, 2012
    Date of Patent: July 7, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Suk-jin Chung, Youn-soo Kim, Cha-young Yoo, Jong-cheol Lee, Sang-yeol Kang
  • Publication number: 20140338600
    Abstract: An exhausting apparatus includes an exhaust pump configured to extract unreacted precursor in a process chamber and vent the unreacted precursor out of the exhaust pump, and a first material supplier configured to supply a first material into the exhaust pump. The first material is adsorbable on an interior surface of the exhaust pump to prevent the unreacted precursor from being adsorbed on the interior surface of the exhaust pump.
    Type: Application
    Filed: April 23, 2014
    Publication date: November 20, 2014
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jong-Cheol LEE, Beom-Seok KIM, Suk-JIn CHUNG, Geun-Kyu CHOI
  • Patent number: 8318560
    Abstract: Methods of forming a capacitor of an integrated circuit device include forming a lower electrode of the capacitor on an integrated circuit substrate without exposing a contact plug to be coupled to the lower electrode. A supporting conductor is formed coupling the lower electrode to the contact plug after forming the lower electrode. A capacitor dielectric layer is formed on the lower electrode and an upper electrode of the capacitor is formed on the capacitor dielectric layer.
    Type: Grant
    Filed: February 28, 2007
    Date of Patent: November 27, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Wan-Don Kim, Cha-Young Yoo, Suk-Jin Chung, Jin-Yong Kim
  • Publication number: 20120276721
    Abstract: A method of forming an oxide layer. The method includes: forming a layer of reaction-inhibiting functional groups on a surface of a substrate; forming a layer of precursors of a metal or a semiconductor on the layer of the reaction-inhibiting functional groups; and oxidizing the precursors of the metal or the semiconductor in order to obtain a layer of a metal oxide or a semiconductor oxide. According to the method, an oxide layer having a high thickness uniformity may be formed and a semiconductor device having excellent electrical characteristics may be manufactured.
    Type: Application
    Filed: April 28, 2012
    Publication date: November 1, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Suk-jin Chung, Jong-cheol Lee, Youn-soo Kim, Cha-young Yoo, Sang-yeol Kang
  • Patent number: 8264026
    Abstract: Nonvolatile memory devices and related methods of manufacturing the same are provided. A nonvolatile memory device includes a tunneling layer on a substrate, a floating gate on the tunneling layer, an inter-gate dielectric layer structure on the floating gate, and a control gate on the inter-gate dielectric layer structure. The inter-gate dielectric layer structure includes a first silicon oxide layer, a high dielectric layer on the first silicon oxide layer, and a second silicon oxide layer on the high dielectric layer opposite to the first silicon oxide layer The high dielectric layer may include first and second high dielectric layers laminated on each other, and the first high dielectric layer may have a lower density of electron trap sites than the second high dielectric layer and may have a larger energy band gap or conduction band-offset than the second high dielectric layer.
    Type: Grant
    Filed: January 27, 2010
    Date of Patent: September 11, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Hae Lee, Byong-Sun Ju, Suk-Jin Chung, Young-Sun Kim
  • Publication number: 20120225548
    Abstract: To form a dielectric layer, an organometallic precursor is adsorbed on a substrate loaded into a process chamber. The organometallic precursor includes a central metal and ligands bound to the central metal. An inactive oxidant is provided onto the substrate. The inactive oxidant is reactive with the organometallic precursor. An active oxidant is also provided onto the substrate. The active oxidant has a higher reactivity than that of the inactive oxidant.
    Type: Application
    Filed: February 21, 2012
    Publication date: September 6, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: SANG-YEOL KANG, SUK-JIN CHUNG, YOUN-SOO KIM, JAE-HYOUNG CHOI, JAE-SOON LIM, MIN-YOUNG PARK
  • Publication number: 20110151639
    Abstract: Provided are a semiconductor device, a method of fabricating the same, and a semiconductor module, an electronic circuit board, and an electronic system including the device. The semiconductor device includes a lower electrode, a rutile state lower vanadium dioxide layer on the lower electrode, a rutile state titanium oxide on the lower vanadium dioxide layer, and an upper electrode on the titanium oxide layer.
    Type: Application
    Filed: August 12, 2010
    Publication date: June 23, 2011
    Inventors: Jae-Soon Lim, Youn-Soo Kim, Jae-Hyoung Choi, Sang-Yeol Kang, Suk-Jin Chung
  • Publication number: 20110136317
    Abstract: Example embodiments relate to a semiconductor device including an oxide dielectric layer and a non-oxide dielectric layer, a method of fabricating the device, and a semiconductor module, an electronic circuit board, and an electronic system including the device. The semiconductor device may include a lower electrode, an oxide dielectric layer disposed on the lower electrode, a non-oxide dielectric layer disposed on the oxide dielectric layer, and an upper electrode disposed on the non-oxide dielectric layer.
    Type: Application
    Filed: March 23, 2010
    Publication date: June 9, 2011
    Inventors: Sang-Yeol Kang, Youn-Soo Kim, Jae-Hyoung Choi, Jae-Soon Lim, Min-Young Park, Suk-Jin Chung
  • Publication number: 20110095397
    Abstract: Semiconductor structures including a first conductive layer; a dielectric layer on the first conductive layer; a second conductive layer on the dielectric layer; and a crystallized seed layer in at least one of a first portion between the first conductive layer and the dielectric layer and a second portion between the dielectric layer and the second conductive layer. Related capacitors and methods are also provided herein.
    Type: Application
    Filed: October 21, 2010
    Publication date: April 28, 2011
    Inventors: Suk-jin Chung, Jae-hyoung Choi, Youn-soo Kim, Jae-soon Lim, Sang-yeol Kang
  • Patent number: 7842581
    Abstract: When a metal layer formed by reaction of a metal source and an oxygen (O2) source is deposited, oxidization of a conductive layer disposed under or on the metal layer can be reduced and/or prevented by a method of forming the metal layer and a method of fabricating a capacitor using the same. Between forming the conductive layer and the metal layer, and between forming the metal layer and the conductive layer, a cycle of supplying a metal source, purging, supplying an oxygen source, purging, plasma processing of reduction gas and purging is repeated at least once. In this case, the metal layer is formed by repeating a cycle of supplying a metal source, purging, supplying an oxygen source and purging.
    Type: Grant
    Filed: December 27, 2006
    Date of Patent: November 30, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Suk-Jin Chung, Jin-Yong Kim, Wan-Don Kim, Kwang-Hee Lee, Cha-Young Yoo
  • Publication number: 20100187595
    Abstract: Nonvolatile memory devices and related methods of manufacturing the same are provided. A nonvolatile memory device includes a tunneling layer on a substrate, a floating gate on the tunneling layer, an inter-gate dielectric layer structure on the floating gate, and a control gate on the inter-gate dielectric layer structure. The inter-gate dielectric layer structure includes a first silicon oxide layer, a high dielectric layer on the first silicon oxide layer, and a second silicon oxide layer on the high dielectric layer opposite to the first silicon oxide layer The high dielectric layer may include first and second high dielectric layers laminated on each other, and the first high dielectric layer may have a lower density of electron trap sites than the second high dielectric layer and may have a larger energy band gap or conduction band-offset than the second high dielectric layer.
    Type: Application
    Filed: January 27, 2010
    Publication date: July 29, 2010
    Inventors: Sung-Hae Lee, Byong-Sun Ju, Suk-Jin Chung, Young-Sun Kim
  • Patent number: 7700454
    Abstract: A method of fabricating a uniformly wrinkled capacitor lower electrode without the need to perform a high-temperature heat treatment and a method of fabricating a capacitor including the uniformly wrinkled capacitor lower electrode are provided. A first conductive layer is formed. Then, a second conductive layer including about 20% to about 50% of impurities is formed on the first conductive layer. Next, at least some of the impurities are exhausted from the second conductive layer by heat treating the second conductive layer. A surface of the second conductive layer is wrinkled due to the exhaustion of the impurities from the second conductive layer. A dielectric layer and an upper capacitor electrode may then be formed.
    Type: Grant
    Filed: August 3, 2006
    Date of Patent: April 20, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Wan-don Kim, Jae-hyun Joo, Seok-jun Won, Jung-hee Chung, Jin-yong Kim, Suk-jin Chung
  • Patent number: 7531861
    Abstract: Trench capacitors that have insulating layer collars in undercut regions and methods of fabricating such trench capacitors are provided. Some methods of fabricating a trench capacitor include forming a first layer on a substrate. A second layer is formed on the first layer opposite to the substrate. A mask is formed that has an opening on top of the first and second layers. A first trench is formed by removing a portion of the first and second layers through the opening in the mask. A portion of the first layer under the second layer is removed to form an undercut region under the second layer. An insulating layer collar is formed in the undercut region under the second layer. A second trench is formed that extends from the first trench by removing a portion of the substrate through the opening in the mask. A buried plate is formed in the substrate along the second trench. A dielectric layer is formed on an inner wall and bottom of the second trench.
    Type: Grant
    Filed: February 19, 2008
    Date of Patent: May 12, 2009
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Suk-jin Chung, Seung-hwan Lee, Sung-tae Kim, Young-sun Kim, Jae-soon Lim, Young-geun Park
  • Patent number: 7416904
    Abstract: A fabrication method for forming a semiconductor device having a capacitor is provided. A capacitor dielectric layer is formed by depositing a first layer and a second layer. The second layer is a major portion of the capacitor dielectric layer. The first layer acts as a seed layer, while the second layer is expitaxially grown. The material of the second layer as deposited is partially crystal. Nuclear generation and crystal growth occur separately so that the crystalline characteristic of the capacitor dielectric layer and the capacitance characteristic of the capacitor are enhanced. Moreover, the capacitor dielectric layer is crystallized at a relatively low temperature or for a relatively short time, thereby reducing leakage current as well as reducing deformation in the lower electrode. Optionally, The material of the second layer as deposited is not partially crystal but amorphous.
    Type: Grant
    Filed: November 12, 2002
    Date of Patent: August 26, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Hyoung Choi, Cha-Young Yoo, Suk-Jin Chung, Wan-Don Kim
  • Publication number: 20080135876
    Abstract: Trench capacitors that have insulating layer collars in undercut regions and methods of fabricating such trench capacitors are provided. Some methods of fabricating a trench capacitor include forming a first layer on a substrate. A second layer is formed on the first layer opposite to the substrate. A mask is formed that has an opening on top of the first and second layers. A first trench is formed by removing a portion of the first and second layers through the opening in the mask. A portion of the first layer under the second layer is removed to form an undercut region under the second layer. An insulating layer collar is formed in the undercut region under the second layer. A second trench is formed that extends from the first trench by removing a portion of the substrate through the opening in the mask. A buried plate is formed in the substrate along the second trench. A dielectric layer is formed on an inner wall and bottom of the second trench.
    Type: Application
    Filed: February 19, 2008
    Publication date: June 12, 2008
    Inventors: Suk-jin Chung, Seung-hwan Lee, Sung-tae Kim, Young-sun Kim, Jae-soon Lim, Young-geun Park