Patents by Inventor SukMin KANG

SukMin KANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11789876
    Abstract: A device including an interface with peripherals includes a first interface that receives a request from a host, a second interface that periodically receives at least one first sample input from the peripherals in response to the request from the host, a memory that stores an active time table including a processing time of a sample input provided by each of the peripherals in each of a plurality of operating conditions respectively corresponding to different power consumptions, and a processing circuit that identifies at least one of the plurality of operating conditions based on the active time table and a period of the at least one first sample input.
    Type: Grant
    Filed: March 4, 2021
    Date of Patent: October 17, 2023
    Inventors: Boojin Kim, Sukmin Kang, Shinkyu Park, Boyoung Kim, Sukwon Ryoo
  • Publication number: 20220279656
    Abstract: A method of forming a molded interconnect device (MID) is provided. The method includes the steps of performing a molding stage, performing a circuit forming stage, and performing a plate stage. As a part of the molding stage, a palladium-catalyzed material is injection molded into a palladium-catalyzed substrate of a desired shape. As a part of the circuit forming stage, both a metallization step and a circuit patterning step are performed. As a part of the plating stage, both an electrolytic plating step and a circuit isolation step are performed.
    Type: Application
    Filed: May 20, 2022
    Publication date: September 1, 2022
    Applicant: Molex, LLC
    Inventors: Tsuey Choo CHANG, Steven ZEILINGER, Hyun-Jong KO, Patrick RILEY, SukMin KANG
  • Patent number: 11357112
    Abstract: In some embodiments, a manufacturing process includes injection molding a palladium-catalyzed material into a substrate, forming a thin copper film over exterior and exposed surfaces of the substrate; ablating or removing copper film from the substrate to provide first, second and optional third portions of the copper film and ablated sections; electrolytically plating each portion to form metallic-plated portions; and ablating or removing the second portion in order to isolate the first portion. The metallic-plated first portion comprises a circuit portion of a molded interconnect device (MID), and where the metallic-plated third portion comprises a Faraday cage portion of a MID. A soft etching step may be included. A solder resist application step can be added, along with an associated solder resist removal step.
    Type: Grant
    Filed: July 5, 2017
    Date of Patent: June 7, 2022
    Assignee: Molex, LLC
    Inventors: Tsuey Choo Chang, Steven Zeilinger, Hyun-Jong Ko, Patrick Riley, SukMin Kang
  • Publication number: 20220066951
    Abstract: A device including an interface with peripherals includes a first interface that receives a request from a host, a second interface that periodically receives at least one first sample input from the peripherals in response to the request from the host, a memory that stores an active time table including a processing time of a sample input provided by each of the peripherals in each of a plurality of operating conditions respectively corresponding to different power consumptions, and a processing circuit that identifies at least one of the plurality of operating conditions based on the active time table and a period of the at least one first sample input.
    Type: Application
    Filed: March 4, 2021
    Publication date: March 3, 2022
    Inventors: BOOJIN KIM, SUKMIN KANG, SHINKYU PARK, BOYOUNG KIM, SUKWON RYOO
  • Publication number: 20190166698
    Abstract: In some embodiments, a manufacturing process includes injection molding a palladium-catalyzed material into a substrate, forming a thin copper film over exterior and exposed surfaces of the substrate; ablating or removing copper film from the substrate to provide first, second and optional third portions of the copper film and ablated sections; electrolytically plating each portion to form metallic-plated portions; and ablating or removing the second portion in order to isolate the first portion. The metallic-plated first portion comprises a circuit portion of a molded interconnect device (MID), and where the metallic-plated third portion comprises a Faraday cage portion of a MID. A soft etching step may be included. A solder resist application step can be added, along with an associated solder resist removal step.
    Type: Application
    Filed: July 5, 2017
    Publication date: May 30, 2019
    Applicant: Molex, LLC
    Inventors: Tsuey Choo CHANG, Steven ZEILINGER, Hyun-Jong KO, Patrick RILEY, SukMin KANG