Patents by Inventor Sukrutha Bharadwaj Hebbagilu Krishna

Sukrutha Bharadwaj Hebbagilu Krishna has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • System and method for reducing non-linearity in mixed signal processing using complex polynomial vector processor
    Patent number: 10572253
    Abstract: A system for reducing non-linearity in mixed signal processing using complex polynomial vector processor 102 is provided. The complex polynomial vector processor 102 includes a data processing unit (104) and a co-efficient feeder unit (106). The data processing unit (104) converts a high-speed data stream into a polar-like format (PL) data and calculates required polynomial powers for the high-speed data stream using the PL format data. The data processing unit (104) includes a multiplier accumulator (MAC) unit (206) that generates processed high-speed data and a delay unit (208) that combines time separated input with the processed high-speed data to generate output data with reduced non-linearity.
    Type: Grant
    Filed: May 2, 2018
    Date of Patent: February 25, 2020
    Inventors: Himamshu Gopalakrishna Khasnis, Sukrutha Bharadwaj Hebbagilu Krishna
  • SYSTEM AND METHOD FOR REDUCING NON-LINEARITY IN MIXED SIGNAL PROCESSING USING COMPLEX POLYNOMIAL VECTOR PROCESSOR
    Publication number: 20180321941
    Abstract: A system for reducing non-linearity in mixed signal processing using complex polynomial vector processor 102 is provided. The complex polynomial vector processor 102 includes a data processing unit (104) and a co-efficient feeder unit (106). The data processing unit (104) converts a high-speed data stream into a polar-like format (PL) data and calculates required polynomial powers for the high-speed data stream using the PL format data. The data processing unit (104) includes a multiplier accumulator (MAC) unit (206) that generates processed high-speed data and a delay unit (208) that combines time separated input with the processed high-speed data to generate output data with reduced non-linearity.
    Type: Application
    Filed: May 2, 2018
    Publication date: November 8, 2018
    Inventors: Himamshu Gopalakrishna Khasnis, Sukrutha Bharadwaj Hebbagilu Krishna