Patents by Inventor Sukumar Muthusamy

Sukumar Muthusamy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11831477
    Abstract: An information handling system includes a first component including a transmitter for a high-speed serial data interface, and a second component including a receiver for the high-speed serial data interface. The receiver includes an equalization stage and a decision feedback equalization (DFE) stage. The equalization stage has an input to configure the equalization stage in one of a first low equalization state and a first high equalization state. The DFE stage has a plurality of tap inputs. The first component provides a plurality of training runs on the high-speed serial data interface.
    Type: Grant
    Filed: April 4, 2022
    Date of Patent: November 28, 2023
    Assignee: Dell Products L.P.
    Inventors: Vijender Kumar, Douglas Wallace, Bhyrav Mutnury, Sukumar Muthusamy
  • Publication number: 20230325569
    Abstract: An information handling system includes a memory device and a processor. The memory device includes first data representing a thermal profile of a motherboard, and second data representing a circuit trace of the motherboard. The circuit trace provides a high-speed data interconnection between two or more circuit devices. The processor determines an average temperature of the circuit trace on the motherboard based upon the first data and the second data, and models a trace layout for the circuit trace on the motherboard based upon the average temperature.
    Type: Application
    Filed: April 8, 2022
    Publication date: October 12, 2023
    Inventors: Vijender Kumar, Mallikarjun Vasa, Ashish Shrivastava, Bhyrav Mutnury, Seema P K, Sukumar Muthusamy, Sanjay Kumar, Sunil Pathania
  • Publication number: 20230318886
    Abstract: An information handling system includes a first component including a transmitter for a high-speed serial data interface, and a second component including a receiver for the high-speed serial data interface. The receiver includes an equalization stage and a decision feedback equalization (DFE) stage. The equalization stage has an input to configure the equalization stage in one of a first low equalization state and a first high equalization state. The DFE stage has a plurality of tap inputs. The first component provides a plurality of training runs on the high-speed serial data interface.
    Type: Application
    Filed: April 4, 2022
    Publication date: October 5, 2023
    Inventors: Vijender Kumar, Douglas Wallace, Bhyrav Mutnury, Sukumar Muthusamy