Abstract: An order management tool, method, and system are disclosed. The order management tool can use clusters of two or more locations to generate fulfillment plans for orders. The order management tool can determine whether a cluster can fulfill an order and, if so, can determine, for each item of an order, a location within the cluster from which to send the item. The items may be consolidated at a sortation center. The locations can be stores and the clusters can cover a geographical area. The order management tool can also generate two fulfillment plans, one of which allocates the order within the cluster and one of which may use one or more locations outside of the cluster, and the order management tool can apply rules to compare the two fulfillment plans and select one of them.

Abstract: Determining optical visibility in an environment that may contain airborne dust particles is described. In one aspect, a method determines an ambient relative humidity in the environment. A near infrared wave is transmitted through a portion of the environment. An optical visibility in the environment is calculated based on the ambient relative humidity and attenuation of the near infrared wave during transmission through the environment. Various contrast thresholds are employed in the determination of optical visibility in the environment.

Abstract: Determining optical visibility in an environment that may contain airborne dust particles is described. In one aspect, a method determines an ambient relative humidity in the environment. A near infrared wave is transmitted through a portion of the environment. An optical visibility in the environment is calculated based on the ambient relative humidity and attenuation of the near infrared wave during transmission through the environment. Various contrast thresholds are employed in the determination of optical visibility in the environment.

Abstract: A memory cache method and apparatus with two memory execution pipelines, each having a translation lookaside buffer (TLB). Memory instructions are executed in the first pipeline (324) by searching a data cache (310) and a prefetch cache (320). A large data TLB (330) provides memory for storing address translations for the first pipeline (324) A second pipeline (328) executes memory instructions by accessing the prefetch cache (320). A second micro-TLB (340) is associated with the second pipeline (328). It is loaded in anticipation of data that will be referenced by the second pipeline (328). A history file (360) is also provided to retain information on previous instructions to aid in deciding when to prefetch data. Prefetch logic (370) determines when to prefetch data, and steering logic (380) routes certain instructions to the second pipeline (328) to increase system performance.

Abstract: A memory cache method and apparatus with two memory execution pipelines, each having a translation lookaside buffer (TLB). Memory instructions are executed in the first pipeline (324) by searching a data cache (310) and a prefetch cache (320). A large data TLB (330) provides memory for storing address translations for the first pipeline (324) A second pipeline (328) executes memory instructions by accessing the prefetch cache (320). A second micro-TLB (340) is associated with the second pipeline (328). It is loaded in anticipation of data that will be referenced by the second pipeline (328). A history file (360) is also provided to retain information on previous instructions to aid in deciding when to prefetch data. Prefetch logic (370) determines when to prefetch data, and steering logic (380) routes certain instructions to the second pipeline (328) to increase system performance.

Abstract: A system and method are provided for controlling the generation of assembly language sequences. This is accomplished with a high level language which has as data types various elements of assembly language syntax. Included among the data types are "instructions" data types which specify variables having one or more assembly language instructions, e.g., floating point addition, integer load, conditional branch, etc. The grammar of the high level language permits variables of data type "instruction" to be output in standard assembly language syntax. By incorporating variables of assembly language data types, the language allows programmers employing functions, branch control, and other commonly employed programming techniques to write a programs which generate a large number of assembly language instructions in a controlled sequence.

Abstract: A machine instruction generator which generates a sequence of processor test instructions by traversing sites on a network, each of which has a local state corresponding to a group of related machine instructions. The sequence of processor instructions are generated by selecting a site on the network, randomly selecting a machine instruction available at that site by virtue of the local state, adding that machine instruction to a diagnostic file, and moving to an adjacent site. The sequence of machine instructions is concurrently tested on a functional model of the processor and a logical design of the processor. Any discrepancy in the results of these two tests indicates that a bug has been found in the processor. Network paths leading to the discovery of processor bugs may be represented in new generation networks produced by reinforcement learning or genetic operations.