Patents by Inventor Sum-Min Wang

Sum-Min Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110057321
    Abstract: A 3-D multi-wafer stacked semiconductor structure and method for manufacturing the same. The method comprises steps of: providing a first wafer, a first circuit layer being formed on a surface thereof; bonding the first circuit layer with a carrier; performing a first thinning process on the first wafer; forming a first mask on the other surface of the thinned first wafer; providing a second wafer, a second circuit layer being formed on a surface thereof; bonding the second circuit layer with the first mask; and forming at least a through via filled with a conductor to electrically connect a first connecting pad on the first circuit layer and a second connecting pad on the second circuit layer.
    Type: Application
    Filed: August 25, 2010
    Publication date: March 10, 2011
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Sum-Min Wang, Shih-Hui Wang, Dun-Ying Shu, Chwan-Ying Lee