Abstract: A semiconductor memory device having an internal circuit which is powered from a first power source terminal and outputs an output drive signal corresponding to a stored data in a selected memory cell of a memory cell array; and output buffer unit which is powered from a second power source terminal and operates in such a manner that a gate is closed or opened in accordance with whether the output drive signal is low level or high level, and an output signal of low level or high level corresponding to closed gate or opened gate is outputted via an external output terminal to the external; and a level change suppressing circuit for suppressing a level change of the output drive signal as viewed from the output buffer, by connecting the output terminal of the internal circuit to one of the second power source terminal and the external output terminal, when the potential at the second power source terminal changes relatively with respect to the potential at the first power source terminal as the output signal at