Patents by Inventor SUMAN AMUGOTHU

SUMAN AMUGOTHU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11868779
    Abstract: Aspects of the invention include a computer-implemented method of updating metadata prediction tables. The computer-implemented method includes establishing, in the metadata prediction tables, a prediction of how a set of instructions will resolve and identifying that the set of instructions is completed. The computer-implemented method also includes determining, upon completion of the set of instructions, whether prediction update queues (PUQs) associated with the set of instructions indicate that the set of instructions resolved in one of a plurality of prescribed manners relative to the prediction and deciding that the metadata predictions tables are candidates to be updated based on the PUQs indicating that the set of instructions resolved in one of the plurality of prescribed manners.
    Type: Grant
    Filed: September 9, 2021
    Date of Patent: January 9, 2024
    Assignee: International Business Machines Corporation
    Inventors: James Raymond Cuffney, Adam Benjamin Collura, James Bonanno, Brian Robert Prasky, Edward Thomas Malley, Suman Amugothu
  • Publication number: 20230075992
    Abstract: Aspects of the invention include a computer-implemented method of updating metadata prediction tables. The computer-implemented method includes establishing, in the metadata prediction tables, a prediction of how a set of instructions will resolve and identifying that the set of instructions is completed. The computer-implemented method also includes determining, upon completion of the set of instructions, whether prediction update queues (PUQs) associated with the set of instructions indicate that the set of instructions resolved in one of a plurality of proscribed manners relative to the prediction and deciding that the metadata predictions tables are candidates to be updated based on the PUQs indicating that the set of instructions resolved in one of the plurality of proscribed manners.
    Type: Application
    Filed: September 9, 2021
    Publication date: March 9, 2023
    Inventors: James Raymond Cuffney, Adam Benjamin Collura, James Bonanno, Brian Robert Prasky, Edward Thomas Malley, Suman Amugothu
  • Patent number: 11163573
    Abstract: A system includes a hierarchical metadata predictor and a processing circuit. The hierarchical metadata predictor includes a first-level metadata predictor and a second-level metadata predictor. The processing circuit is configured to perform a plurality of operations including storing new or updated metadata into the first-level metadata predictor and searching the first-level metadata predictor for a metadata prediction. Responsive to finding the metadata prediction in the first-level metadata predictor, the metadata prediction is output corresponding to an entry of the first-level metadata predictor that is a hit. One or more entries of the first-level metadata predictor that are non-hits are periodically written to the second-level metadata predictor. The first-level metadata predictor is updated based on locating the metadata prediction in the second-level metadata predictor.
    Type: Grant
    Filed: February 13, 2019
    Date of Patent: November 2, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: James Bonanno, Varnika Atmakuri, Adam Collura, Brian Robert Prasky, Anthony Saporito, Suman Amugothu
  • Patent number: 10838659
    Abstract: Examples of techniques for controlling write requests to a memory structure having limited write ports are described herein. An aspect includes storing, in a first queue, write requests received from a first source having a first priority. Another aspect includes storing, in a second queue, write requests received from a second source having a second priority, wherein the second priority is lower than the first priority. Aspects also include identifying a selected queue from the first queue and the second queue based on a selection algorithm, which is a function of a state associated with the first queue and the second queue. Aspects further include forwarding a write request from the selected queue to a write port of the memory structure.
    Type: Grant
    Filed: February 8, 2019
    Date of Patent: November 17, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Varnika Atmakuri, Adam Collura, James Bonanno, Suman Amugothu
  • Publication number: 20200257534
    Abstract: A system includes a hierarchical metadata predictor and a processing circuit. The hierarchical metadata predictor includes a first-level metadata predictor and a second-level metadata predictor. The processing circuit is configured to perform a plurality of operations including storing new or updated metadata into the first-level metadata predictor and searching the first-level metadata predictor for a metadata prediction. Responsive to finding the metadata prediction in the first-level metadata predictor, the metadata prediction is output corresponding to an entry of the first-level metadata predictor that is a hit. One or more entries of the first-level metadata predictor that are non-hits are periodically written to the second-level metadata predictor. The first-level metadata predictor is updated based on locating the metadata prediction in the second-level metadata predictor.
    Type: Application
    Filed: February 13, 2019
    Publication date: August 13, 2020
    Inventors: James Bonanno, Varnika Atmakuri, Adam Collura, Brian Robert Prasky, Anthony Saporito, Suman Amugothu
  • Publication number: 20200257468
    Abstract: Examples of techniques for controlling write requests to a memory structure having limited write ports are described herein. An aspect includes storing, in a first queue, write requests received from a first source having a first priority. Another aspect includes storing, in a second queue, write requests received from a second source having a second priority, wherein the second priority is lower than the first priority. Aspects also include identifying a selected queue from the first queue and the second queue based on a selection algorithm, which is a function of a state associated with the first queue and the second queue. Aspects further include forwarding a write request from the selected queue to a write port of the memory structure.
    Type: Application
    Filed: February 8, 2019
    Publication date: August 13, 2020
    Inventors: VARNIKA ATMAKURI, ADAM COLLURA, JAMES BONANNO, SUMAN AMUGOTHU