Abstract: Wideband capacitive sensing (single-ended or differential) is based on a modulated sense (capacitance) signal. A carrier/drive signal path modulates a reference signal with a carrier signal (such as fixed frequency or spread spectrum) to generate a carrier/drive signal, driven (with optional pre-scaling) out through an output node (to sense capacitor(s)). A sense signal path receives at an input/summing node up-modulated sense capacitance signal(s), corresponding to measured capacitance up-modulated to the carrier frequency, and, after filtering (optional) and amplification, demodulates the up-modulated sense capacitance signal with the carrier signal, to generate a demodulated sense capacitance signal corresponding to measured capacitance, which can be converted to sensor data. Sense signal path amplification can use charge amplification (capacitor feedback), or transimpedance amplification (resistor feedback).

Abstract: Provided are methods and systems for performing binary data conversion in digital-to-analog converters (DACs) having sigma-delta modulators and involving data directed scrambling (DDS) algorithms to effectively shape the element mismatch errors to first-order shaped wideband noise. An example method may commence with receiving binary data, which comprises positive binary data and negative binary data. The method may further comprise converting, by a DDS unit, the binary data into binary thermometer code data. The conversion is performed by selectively assigning one or more logic ones in a data array from a current location of a positive (negative) pointer when positive (negative) binary data is received. A number of the one or more logic ones may be associated with the binary data. The method may further comprise circularly shifting the positive (negative) pointer to a new location within the array by the number of the one or more logic ones.

Abstract: A rail-to-rail amplifier is provided. The rail-to-rail amplifier includes a p-type differential pair, an n-type differential pair, switches, and an output stage. The switches are arranged to selectively couple either the p-type differential pair or the n-type differential pair to the output stage so that only one of the differential pairs is coupled to the output stage at a time.

Abstract: A circuit for reducing EMI is provided. The circuit includes driver circuitry that drives a power switch, such as a power MOSFET. The power switch provides an output voltage. The circuit decreases the drive strength by which the power switch is driven during each output edge (i.e. when the output goes from low to high (rising edge) or high to low (falling edge)), and returns the drive strength to its normal level when the output edge is complete or approximately complete. Reducing the drive strength of the driver circuitry causes the output edge to occur over a longer period of time. This results in reduction of the EMI of the device.

Abstract: An input stage for an audio power amplifier is provided. The input stage includes a fully differential amplifier and a supply-independent reference voltage generator. The supply-independent reference voltage generator provides a supply-independent reference voltage that is used as the common mode voltage of the output of the fully differential amplifier.

Abstract: A rail-to-rail amplifier is provided. The rail-to-rail amplifier includes a p-type differential pair, an n-type differential pair, switches, and an output stage. The switches are arranged to selectively couple either the p-type differential pair or the n-type differential pair to the output stage so that only one of the differential pairs is coupled to the output stage at a time.

Abstract: A circuit for reducing EMI is provided. The circuit includes driver circuitry that drives a power switch, such as a power MOSFET. The power switch provides an output voltage. The circuit decreases the drive strength by which the power switch is driven during each output edge (i.e. when the output goes from low to high (rising edge) or high to low (falling edge)), and returns the drive strength to its normal level when the output edge is complete or approximately complete. Reducing the drive strength of the driver circuitry causes the output edge to occur over a longer period of time. This results in reduction of the EMI of the device.

Abstract: A fully differential class D amplifier is provided. The class D amplifier includes an active amplifier in the feedback path of the modulator. In one embodiment, the class D amplifier includes a fully differential amplifier as an input buffer, in which a supply-independent reference voltage is used as the common mode voltage of the output of the fully differential amplifier. In one embodiment, the class D amplifier includes a pulse width modulation circuit that includes rail-to-rail comparators.

Abstract: A circuit for adaptively adjusting the drive strength of output power transistors in a class D amplifier is provided. The circuit includes a driver circuit and a low-voltage detect circuit. The low-voltage detect circuit is arranged to assert a low-voltage detect signal if a low supply voltage condition is detected. The driver circuit is arranged to increase the drive strength if the low-voltage detect signal is asserted. The driver circuit includes a first driver and a second driver. The second driver is enabled if the low-voltage detect signal is asserted, and disabled if the low-voltage detect signal is unasserted.

Abstract: A class D power amplifier is provided to drive a low impedance load for audio applications. The amplifier includes a sigma-delta modulator circuit including three or more integrators that are arranged for third or higher order sigma-delta modulation. Also, the sigma-delta modulator circuit includes a quantizer circuit that is arranged to provide a sigma-delta modulator output signal based on a three-level switching scheme. The class D power amplifier drives a speaker based on the three-level switching scheme so that the output switches between three levels: VDD, 0, and ?VDD, based on the input signal.

Abstract: The test system and method described herein reduces the production test time of semiconductor devices. More specifically, the apparatus method in accordance with the present invention reduces the data transfer time between the test body and the test mainframe. The test system includes a workstation, a handling device, a test body and a test mainframe. A communication channel links the workstation, the handling device, the test body and the test mainframe together for transferring control signals and data. The test mainframe sends control signals to the test body to send a m-bit packet of least significant bits for each n-bit code word, where m is proportional to the noise amplitude inherent in the system in terms of least significant bits. In the alternative, a user at the workstation can send control signals to the test body to send a m-bit packet for each n-bit code word.

Abstract: The test system and method described herein reduces the production test time of semiconductor devices. More specifically, the apparatus method in accordance with the present invention reduces the data transfer time between the test body and the test mainframe. The test system includes a workstation, a handling device, a test body and a test mainframe. A communication channel links the workstation, the handling device, the test body and the test mainframe together for transferring control signals and data. The test mainframe sends control signals to the test body to send a m-bit packet of least significant bits for each n-bit code word, where m is proportional to the noise amplitude inherent in the system in terms of least significant bits. In the alternative, a user at the workstation can send control signals to the test body to send a m-bit packet for each n-bit code word.