Abstract: Methods and apparatus for common-mode current removal in a digital-to-analog converter (DAC). An example DAC circuit generally includes a plurality of current-steering cells, a resistor ladder circuit coupled to the plurality of current-steering cells and having a plurality of shunt branches, and an adjustable resistance circuit coupled between middle nodes of the plurality of shunt branches and a reference potential node for the DAC circuit.

Abstract: A lookahead pipelined ADC architecture uses open-loop residue amplifiers with calibration. This approach is able to achieve a high-speed, high-accuracy ADC with reduced power consumption. In one aspect, an ADC pipeline unit includes a plurality of lookahead pipeline stages (i.e., an ADC lookahead pipeline) coupled to a calibration unit. The ADC lookahead pipeline uses open-loop residue amplifiers. The calibration unit compensates for non-linearity in the open-loop amplifiers.

Abstract: A lookahead pipelined ADC architecture uses open-loop residue amplifiers with calibration. This approach is able to achieve a high-speed, high-accuracy ADC with reduced power consumption. In one aspect, an ADC pipeline unit includes a plurality of lookahead pipeline stages (i.e., an ADC lookahead pipeline) coupled to a calibration unit. The ADC lookahead pipeline uses open-loop residue amplifiers. The calibration unit compensates for non-linearity in the open-loop amplifiers.

Abstract: A multi-threshold flip-flop includes a master latch, a slave latch, and at least one control switch. The master latch is composed of an input buffer formed with low threshold (LVT) transistors and a first latch circuit formed with LVT transistors. The slave latch is composed of a second latch circuit formed with high threshold (HVT) transistors and an output driver formed with LVT transistors. The at least one control switch enables or disables the LVT transistors and is implemented with at least one HVT transistor. The LVT and HVT transistors may be N-FETs and/or P-FETs. The multi-threshold flip-flop can operate at high speed, has low leakage current, and can save the logic state when disabled.

Abstract: A multi-threshold flip-flop includes a master latch, a slave latch, and at least one control switch. The master latch is composed of an input buffer formed with low threshold (LVT) transistors and a first latch circuit formed with LVT transistors. The slave latch is composed of a second latch circuit formed with high threshold (HVT) transistors and an output driver formed with LVT transistors. The at least one control switch enables or disables the LVT transistors and is implemented with at least one HVT transistor. The LVT and HVT transistors may be N-FETs and/or P-FETs. The multi-threshold flip-flop can operate at high speed, has low leakage current, and can save the logic state when disabled.

Abstract: Systems and techniques are disclosed relating to shifting a plurality of input data bits to the left or right by a number of bit positions as a function of a binary value of a plurality of shift control bits. A first shifter element may be configured to perform one of two shifting operations on the input data bits to produce a plurality of first output bits, a first one of the shift control bits being used to select the shifting operation performed by the first shifter element. A second shifter element may be configured to perform at least one shifting operation on the first output bits to produce a plurality of second output bits, each of said at least one shifting operation being selectable from two shifting operations, a different one of the shift control bits being used to select each of said at least one shifting operation performed by the second shifter element.

Abstract: A circuit and method for reducing power in a memory, such as an instruction cache, having a number of blocks, are disclosed. A power reduction signal (also called a “same block” signal) is generated. The power reduction signal indicates whether a subsequent instruction to be fetched from an instruction cache belongs in the same block as a previous instruction fetched from the same instruction cache. When the subsequent instruction belongs to the same block as the previous instruction, there is no need to perform a tag read or an instruction read from an instruction cache other than the same instruction cache which contains the block to which the subsequent instruction belongs, whereby a tag from a tag memory bank is not read when the power reduction signal is in a first logical state.