Patents by Inventor Sumant Tapas

Sumant Tapas has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Technology for optimizing hybrid processor utilization
    Patent number: 11531563
    Abstract: A data processing system comprises a hybrid processor comprising a big TPU and a small TPU. At least one of the TPUs comprises an LP of a processing core that supports SMT. The hybrid processor further comprises hardware feedback circuitry. A machine-readable medium in the data processing system comprises instructions which, when executed, enable an OS in the data processing system to collect (a) processor topology data from the hybrid processor and (b) hardware feedback for at least one of the TPUs from the hardware feedback circuitry. The instructions also enable the OS to respond to a determination that a thread is ready to be scheduled by utilizing (a) an OP setting for the ready thread, (b) the processor topology data, and (c) the hardware feedback to make a scheduling determination for the ready thread. Other embodiments are described and claimed.
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: December 20, 2022
    Assignee: Intel Corporation
    Inventors: Monica Gupta, Eliezer Weissmann, Hisham Abu Salah, Rajshree Arun Chabukswar, Russell Jerome Fenger, Eugene Gorbatov, Guruprasad Settuvalli, Balaji Masanamuthu Chinnathurai, Sumant Tapas, Meghana Gudaram, Raj Kumar Subramaniam
  • Technology For Optimizing Hybrid Processor Utilization
    Publication number: 20210406060
    Abstract: A data processing system comprises a hybrid processor comprising a big TPU and a small TPU. At least one of the TPUs comprises an LP of a processing core that supports SMT. The hybrid processor further comprises hardware feedback circuitry. A machine-readable medium in the data processing system comprises instructions which, when executed, enable an OS in the data processing system to collect (a) processor topology data from the hybrid processor and (b) hardware feedback for at least one of the TPUs from the hardware feedback circuitry. The instructions also enable the OS to respond to a determination that a thread is ready to be scheduled by utilizing (a) an OP setting for the ready thread, (b) the processor topology data, and (c) the hardware feedback to make a scheduling determination for the ready thread. Other embodiments are described and claimed.
    Type: Application
    Filed: June 26, 2020
    Publication date: December 30, 2021
    Inventors: Monica Gupta, Eliezer Weissmann, Hisham Abu Salah, Rajshree Arun Chabukswar, Russell Jerome Fenger, Eugene Gorbatov, Guruprasad Settuvalli, Balaji Masanamuthu Chinnathurai, Sumant Tapas, Meghana Gudaram, Raj Kumar Subramaniam