Patents by Inventor Sumanth Katte Gururajarao
Sumanth Katte Gururajarao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10275010Abstract: A method of detecting and preventing over current induced system failure is provided. An OC protect controller monitors a CPU total power consumption based on received CPU activity information. In response to the monitoring, if the CPU power consumption is over a threshold, then the OC protect controller outputs a frequency dithering control signal to reduce the CPU clock frequency such that the CPU does not reach an OC limit. The OC protect controller also outputs a PLL frequency control signal to reduce the PLL clock frequency to improve system efficiency.Type: GrantFiled: February 16, 2015Date of Patent: April 30, 2019Assignee: MediaTek Singapore Pte. Ltd.Inventors: Hugh Thomas Mair, Sumanth Katte Gururajarao, Gordon Gammie, Alice Wang, Uming Ko, Rolf Lagerquist
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Publication number: 20170068296Abstract: A method of detecting and preventing over current induced system failure is provided. An OC protect controller monitors a CPU total power consumption based on received CPU activity information. In response to the monitoring, if the CPU power consumption is over a threshold, then the OC protect controller outputs a frequency dithering control signal to reduce the CPU clock frequency such that the CPU does not reach an OC limit. The OC protect controller also outputs a PLL frequency control signal to reduce the PLL clock frequency to improve system efficiency.Type: ApplicationFiled: February 16, 2015Publication date: March 9, 2017Inventors: Hugh Thomas Mair, Sumanth Katte Gururajarao, Gordon Gammie, Alice Wang, Uming Ko, Rolf Lagerquist
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Patent number: 9148145Abstract: A clock gating circuit for generating a clock enable signal with respect to a clock input signal and a logic enable signal includes: a first plurality of transistors coupled in series between a power supply and ground, for receiving at least the logic enable signal and generating a first output; a second plurality of transistor coupled in series between the power supply and ground, for receiving at least the first output and generating a second output; a third plurality of transistors coupled in series between the power supply and ground, for receiving at least the second output and an inverted second output; and an AND gate circuit, for receiving the second output and generating the clock enable signal.Type: GrantFiled: February 9, 2015Date of Patent: September 29, 2015Assignee: MediaTek Singapore Pte. Ltd.Inventor: Sumanth Katte Gururajarao
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Publication number: 20150155870Abstract: A clock gating circuit for generating a clock enable signal with respect to a clock input signal and a logic enable signal includes: a first plurality of transistors coupled in series between a power supply and ground, for receiving at least the logic enable signal and generating a first output; a second plurality of transistor coupled in series between the power supply and ground, for receiving at least the first output and generating a second output; a third plurality of transistors coupled in series between the power supply and ground, for receiving at least the second output and an inverted second output; and an AND gate circuit, for receiving the second output and generating the clock enable signal.Type: ApplicationFiled: February 9, 2015Publication date: June 4, 2015Inventor: Sumanth Katte Gururajarao
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Patent number: 8981815Abstract: A clock gating circuit for generating a clock enable signal with respect to a clock input signal and a logic enable signal includes: a first plurality of transistors for receiving at least the logic enable signal and generating a first output; a second plurality of transistor for receiving at least the first output and generating a second output; a third plurality of transistors for receiving at least the second output and an inverted second output; and an AND gate circuit, for receiving the second output and generating the clock enable signal when the logic enable signal is at logic 1. One transistor of the first plurality of transistors, the second plurality of transistors and the third plurality of transistors, respectively, receives the clock input signal at its gate.Type: GrantFiled: March 19, 2014Date of Patent: March 17, 2015Assignee: MediaTek Singapore Pte. Ltd.Inventor: Sumanth Katte Gururajarao
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Publication number: 20140292372Abstract: A clock gating circuit for generating a clock enable signal with respect to a clock input signal and a logic enable signal includes: a first plurality of transistors for receiving at least the logic enable signal and generating a first output; a second plurality of transistor for receiving at least the first output and generating a second output; a third plurality of transistors for receiving at least the second output and an inverted second output; and an AND gate circuit, for receiving the second output and generating the clock enable signal when the logic enable signal is at logic 1. One transistor of the first plurality of transistors, the second plurality of transistors and the third plurality of transistors, respectively, receives the clock input signal at its gate.Type: ApplicationFiled: March 19, 2014Publication date: October 2, 2014Applicant: MediaTek Singapore Pte. Ltd.Inventor: Sumanth Katte Gururajarao
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Patent number: 7652513Abstract: In a method and apparatus for data retention, a first latch latches a data input and a second latch that is coupled to the first latch retains the data input while the first latch is inoperative in a standby power mode. The second latch includes a second latch inverter having an inverter input and an inverter output. A switching circuit, which may be implemented as a tristate inverter, is coupled to the inverter output, the inverter input, and a retention signal. The switching circuit is operable in the standby power mode to assert a logic state at the inverter input responsive to the retention signal. The logic state is in accordance with the data input retained in the standby power mode. A standby power source is operable to provide power in the standby power mode to the second latch inverter, the switching circuit and the retention input.Type: GrantFiled: August 27, 2007Date of Patent: January 26, 2010Assignee: Texas Instruments IncorporatedInventors: Bindu Prabhakar Rao, Sumanth Katte Gururajarao, Dharin N. Shah
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Patent number: 7639056Abstract: In a method and system for data retention, a data input is latched by a first latch. A second latch coupled to the first latch receives the data input for retention while the first latch is inoperative in a standby power mode. The first latch receives power from a first power line that is switched off during the standby power mode. The second latch receives power from a second power line. A controller receives a clock input and a retention signal and provides a clock output to the first latch and the second latch. A change in the retention signal is indicative of a transition to the standby power mode. The controller continues to hold the clock output at a predefined voltage level and the second latch continues to receive power from the second power line in the standby power mode, thereby retaining the data input.Type: GrantFiled: May 26, 2005Date of Patent: December 29, 2009Assignee: Texas Instruments IncorporatedInventors: Sumanth Katte Gururajarao, Hugh T. Mair, David B. Scott, Uming Ko
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Patent number: 7622955Abstract: An apparatus for providing active mode power reduction for circuits having data retention includes a master slave flip flop (MSFF) for latching a data input. An output level shifter (OLS), coupled to the MSFF, retains the data input in response to the MSFF being operable in an active power saving mode (APSM) to reduce power. The OLS operating in the APSM provides a level shifter output having a configurable voltage, thereby providing output isolation. A change in an operating mode of the MSFF between an active mode and the APSM is independent of a retention (RET) mode input.Type: GrantFiled: April 17, 2008Date of Patent: November 24, 2009Assignee: Texas Instruments IncorporatedInventors: Ramaprasath Vilangudipitchai, Sumanth Katte Gururajarao, Hugh T. Mair, Alice Wang, Uming U. Ko, Sushma Honnavara-Prasad
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Publication number: 20090262588Abstract: An apparatus for providing active mode power reduction for circuits having data retention includes a master slave flip flop (MSFF) for latching a data input. An output level shifter (OLS), coupled to the MSFF, retains the data input in response to the MSFF being operable in an active power saving mode (APSM) to reduce power. The OLS operating in the APSM provides a level shifter output having a configurable voltage, thereby providing output isolation. A change in an operating mode of the MSFF between an active mode and the APSM is independent of a retention (RET) mode input.Type: ApplicationFiled: April 17, 2008Publication date: October 22, 2009Inventors: RAMAPRASATH VILANGUDIPITCHAI, Sumanth Katte Gururajarao, Hugh T. Mair, Alice Wang, Uming U. Ko, Sushma Honnavara-Prasad
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Publication number: 20090058484Abstract: In a method and apparatus for data retention, a first latch latches a data input and a second latch that is coupled to the first latch retains the data input while the first latch is inoperative in a standby power mode. The second latch includes a second latch inverter having an inverter input and an inverter output. A switching circuit, which may be implemented as a tristate inverter, is coupled to the inverter output, the inverter input, and a retention signal. The switching circuit is operable in the standby power mode to assert a logic state at the inverter input responsive to the retention signal. The logic state is in accordance with the data input retained in the standby power mode. A standby power source is operable to provide power in the standby power mode to the second latch inverter, the switching circuit and the retention input.Type: ApplicationFiled: August 27, 2007Publication date: March 5, 2009Inventors: Bindu Prabhakar Rao, Sumanth Katte Gururajarao, Dharin N. Shah
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Patent number: 6947310Abstract: Ferroelectric latch type memory devices (102) are provided, comprising an input circuit (110) with first and second internal nodes (N1, N2) coupled with first and second ferroelectric capacitors (CFE1, CFE2), a control circuit (120), a restore circuit (130), and an output circuit (140). The input circuit (110) operates in a first mode to provide the input data state as first and second voltages on the first and second internal nodes (N1, N2), respectively. In a second mode, the input circuit (110) allows the internal nodes (N1, N2) to float, the restore circuit (130) operates to restore the data state from the ferroelectric capacitors (CFE1, CFE2) to the internal nodes (N1, N2), and the output circuit (140) provides a restored data state as an output (OUT).Type: GrantFiled: May 13, 2004Date of Patent: September 20, 2005Assignee: Texas Instruments IncorporatedInventors: Andrew Marshall, Sumanth Katte Gururajarao