Abstract: A clock dithering circuit that provides cancellation of digital noise spurs is disclosed. The clock dithering circuit includes a control unit that receives an input clock. An ICG (integrated clock gating) cell receives the input clock and receives an enable signal from the control unit. The ICG cell generates a gated clock. A coarse dither unit receives the gated clock and receives a coarse select signal from the control unit. The coarse dither unit generates a coarse dither clock. A fine dither unit receives the coarse dither clock and receives a fine select signal from the control unit. The fine dither unit generates a fine dither clock.

Abstract: A clock dithering circuit that provides cancellation of digital noise spurs is disclosed. The clock dithering circuit includes a control unit that receives an input clock. An ICG (integrated clock gating) cell receives the input clock and receives an enable signal from the control unit. The ICG cell generates a gated clock. A coarse dither unit receives the gated clock and receives a coarse select signal from the control unit. The coarse dither unit generates a coarse dither clock. A fine dither unit receives the coarse dither clock and receives a fine select signal from the control unit. The fine dither unit generates a fine dither clock.

Abstract: A circuit that facilitates faster diagnosis of plurality of logic circuits connected in a scan chain is provided. The circuit includes a first multiplexer that receives a scan data input. A flip-flop is coupled to an output of the first multiplexer and generates a scan pattern. An inverter generates an inverted feedback signal in response to the scan pattern. The inverted feedback signal is provided to the first multiplexer. A plurality of logic circuits is connected in a scan chain and generates a logic output in response to the scan pattern. A bypass multiplexer is coupled to the plurality of logic circuits. The bypass multiplexer generates a scan output in response to the logic output, the scan data input and a segment bypass input.

Abstract: A circuit that facilitates faster diagnosis of plurality of logic circuits connected in a scan chain is provided. The circuit includes a first multiplexer that receives a scan data input. A flip-flop is coupled to an output of the first multiplexer and generates a scan pattern. An inverter generates an inverted feedback signal in response to the scan pattern. The inverted feedback signal is provided to the first multiplexer. A plurality of logic circuits is connected in a scan chain and generates a logic output in response to the scan pattern. A bypass multiplexer is coupled to the plurality of logic circuits. The bypass multiplexer generates a scan output in response to the logic output, the scan data input and a segment bypass input.

Abstract: Apparatuses and methods for suppressing power supply noise harmonics are disclosed. A method includes selecting at least one flip-flop of a plurality of data paths of an integrated circuit based on a slack associated with the at least one flip-flop. The method also includes providing at least one delay circuit at an output of at least one flip-flop. The at least one delay circuit is configured to delay the output of the at least one flip-flop by a threshold clock cycle for managing current at a positive edge of a clock input and current at a negative edge of the clock input, thereby suppressing power supply noise harmonics of the integrated circuit.

Abstract: Apparatuses and methods for suppressing power supply noise harmonics are disclosed. A method includes selecting at least one flip-flop of a plurality of data paths of an integrated circuit based on a slack associated with the at least one flip-flop. The method also includes providing at least one delay circuit at an output of at least one flip-flop. The at least one delay circuit is configured to delay the output of the at least one flip-flop by a threshold clock cycle for managing current at a positive edge of a clock input and current at a negative edge of the clock input, thereby suppressing power supply noise harmonics of the integrated circuit.

Abstract: A circuit for mitigating hold closure. The circuit includes a flip-flop having a clock input and an output. The circuit also includes a multiplexer. The multiplexer includes a select input coupled to the clock input of the flip-flop. The multiplexer also includes a first data input coupled to the output of the flip-flop. Further, the multiplexer includes an output coupled to a second data input of the multiplexer.