Abstract: A semiconductor device includes a cell transistor coupled to a bitline, a bias transistor coupled to the bitline and to a bias node, and a clamp transistor coupled between the bitline and a clamp node. A memory circuit includes an array of memory cell transistors coupled to respective bitlines, bias transistors having a source, a drain, and a gate, the source of each bias transistor coupled to a respective one of the bitlines, a bias node coupled to the gates of the bias transistors, a current source having first and second terminals, the first terminal coupled to the bias node, and the second terminal coupled to a reference node, and clamp transistors, each having a source, a drain, and a gate, the gate and source of each clamp transistor coupled to a respective one of the bitlines, and the drain of each clamp transistor coupled to a clamp node.