Patents by Inventor Sumantha Manoor Madhyastha

Sumantha Manoor Madhyastha has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Stackable timer
    Patent number: 11876518
    Abstract: An system-on-a-chip (“SoC”) is provided. In some examples, the SoC includes a processor and a plurality of timer circuit blocks including at least a first timer circuit block and a second timer circuit block. Each of the plurality of timer circuit blocks may be selectively coupled by at least one of a first programmable matrix and a second programmable matrix. In some examples, the first programmable matrix may be configured to couple a second trigger input of the first timer circuit block with a first trigger output of the second timer circuit block. In some examples, the second programmable matrix is configured to couple a second fault input of the first timer circuit block with a first fault output of the second timer circuit block.
    Type: Grant
    Filed: September 1, 2021
    Date of Patent: January 16, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Rakesh Hariharan, Sumantha Manoor Madhyastha
  • STACKABLE TIMER
    Publication number: 20220200599
    Abstract: An system-on-a-chip (“SoC”) is provided. In some examples, the SoC includes a processor and a plurality of timer circuit blocks including at least a first timer circuit block and a second timer circuit block. Each of the plurality of timer circuit blocks may be selectively coupled by at least one of a first programmable matrix and a second programmable matrix. In some examples, the first programmable matrix may be configured to couple a second trigger input of the first timer circuit block with a first trigger output of the second timer circuit block. In some examples, the second programmable matrix is configured to couple a second fault input of the first timer circuit block with a first fault output of the second timer circuit block.
    Type: Application
    Filed: September 1, 2021
    Publication date: June 23, 2022
    Inventors: Rakesh Hariharan, Sumantha Manoor Madhyastha
  • Stackable timer
    Patent number: 11133804
    Abstract: An system-on-a-chip (“SoC”) is provided. In some examples, the SoC includes a processor and a plurality of timer circuit blocks including at least a first timer circuit block and a second timer circuit block. Each of the plurality of timer circuit blocks may be selectively coupled by at least one of a first programmable matrix and a second programmable matrix. In some examples, the first programmable matrix may be configured to couple a second trigger input of the first timer circuit block with a first trigger output of the second timer circuit block. In some examples, the second programmable matrix is configured to couple a second fault input of the first timer circuit block with a first fault output of the second timer circuit block.
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: September 28, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Rakesh Hariharan, Sumantha Manoor Madhyastha