Abstract: Managing system memory allocation according to a thermal profile defining memory segment policies according to power, performance, and thermal requirements, selecting a defined memory segment policy, implementing a system workload according to the memory segment policy and deploying the system workload according to the implemented memory segment policy.

Abstract: Systems, methods, and computer program products for buffer management in a memory device are provided. Aspects include receiving, by a controller, a request to write a first data to a memory device, analyzing, by the controller, the first data to determine a data type for the first data, obtaining, by the controller, one or more input parameters associated with the memory device, and based on at least one of the one or more input parameters exceeding a first threshold, writing the first data to a write credit buffer.

Abstract: Managing system memory allocation according to a thermal profile defining memory segment policies according to power, performance, and thermal requirements, selecting a defined memory segment policy, implementing a system workload according to the memory segment policy and deploying the system workload according to the implemented memory segment policy.

Abstract: Techniques for a combined voltage translator and latch circuit. The circuit translates a signal from a first voltage domain in an integrated circuit to a second voltage domain in the integrated circuit and acts as a latch for the signal. The circuit includes a regenerative feedback loop, including an input node an output node, a first inverter, and a first transistor. The input node is coupled to the first transistor and an input of the first inverter. The output node is coupled to an output of the first inverter and a gate of the first transistor.

Abstract: Aspects include performing integrated circuit design. A processor identifies a child block of an integrated circuit for placement of a buffer-bay to insert a buffer in a portion of the integrated circuit reserved for the child block. The buffer-bay is divided into a plurality of buffer-bay segments. Parent-level routing information and one or more boundary conditions are analyzed to determine a plurality of placement options for the buffer-bay segments. A best possible placement is selected from the plurality of placement options for the buffer-bay segments as a planned buffer-bay layout. A routing of the integrated circuit is performed based on the planned buffer-bay layout.

Abstract: Systems, methods, and computer program products for buffer management in a memory device are provided. Aspects include receiving, by a controller, a request to write a first data to a memory device, analyzing, by the controller, the first data to determine a data type for the first data, obtaining, by the controller, one or more input parameters associated with the memory device, and based on at least one of the one or more input parameters exceeding a first threshold, writing the first data to a write credit buffer.

Abstract: Aspects include performing integrated circuit design. A processor identifies a child block of an integrated circuit for placement of a buffer-bay to insert a buffer in a portion of the integrated circuit reserved for the child block. The buffer-bay is divided into a plurality of buffer-bay segments. Parent-level routing information and one or more boundary conditions are analyzed to determine a plurality of placement options for the buffer-bay segments. A best possible placement is selected from the plurality of placement options for the buffer-bay segments as a planned buffer-bay layout. A routing of the integrated circuit is performed based on the planned buffer-bay layout.

Abstract: Some embodiments include a method for identifying high-temperature regions in a microchip. In some embodiments, the method includes selecting grids on the microchip, wherein each grid includes devices and interconnects connecting the devices. The method can also include determining, for each grid, a temperature factor value based on geometric area of the grid, geometric area occupied by the devices, switching factor of the of the interconnects, and length of the interconnects connecting the devices. The method can also include determining, for each grid, thermal sensitivity for the grid by generating a plot based on a Guassian equation.