Abstract: Thermal management aspects include a serial databus; a central processing unit (CPU); a graphics processing unit (GPU); a neural signal processor (NSP); an always on subsystem (AOSS); the serial databus, the CPU, the GPU, the NSP and the AOSS are implemented on a system on a chip; wherein the CPU includes a first plurality of thermal sensors and a first plurality of controllers, each of the first plurality of thermal sensors is coupled to each of the first plurality of controllers; wherein the NSP includes a second plurality of thermal sensors and a second plurality of controllers, each of the second plurality of thermal sensors is coupled to each of the second plurality of controllers; and wherein the AOSS includes a third plurality of thermal sensors and a third plurality of controllers, each of the third plurality of thermal sensors is coupled to each of the third plurality of controllers.

Abstract: Certain aspects of the present disclosure provide a method for managing power at a wireless device including detecting a power-intensive activity at a first processing system of the wireless device, and signaling a second processing system, in response to the detection, to take action to manage peak power draw of the wireless device.

Abstract: Power monitoring and limiting of processing units in a processor-based system to limit the overall power consumption of the processor-based system. In exemplary aspects, to limit the overall power consumption of the processor-based system while attempting to achieve an optimized performance of all the processing units, an overall power limit budget is allocated for the processing units (“processing unit power limit budget”). The processor-based system is configured to dynamically determine a total processing unit power limit budget available for the processing units based on remaining overall power available not consumed by other power consuming circuits.

Abstract: Thermal management aspects include a serial databus; a central processing unit (CPU); a graphics processing unit (GPU); a neural signal processor (NSP); an always on subsystem (AOSS); the serial databus, the CPU, the GPU, the NSP and the AOSS are implemented on a system on a chip; wherein the CPU includes a first plurality of thermal sensors and a first plurality of controllers, each of the first plurality of thermal sensors is coupled to each of the first plurality of controllers; wherein the NSP includes a second plurality of thermal sensors and a second plurality of controllers, each of the second plurality of thermal sensors is coupled to each of the second plurality of controllers; and wherein the AOSS includes a third plurality of thermal sensors and a third plurality of controllers, each of the third plurality of thermal sensors is coupled to each of the third plurality of controllers.