Abstract: Accessibility in software engineering is treated as expensive, time consuming and hence adoption of accessibility, is a challenge despite stringent timelines and regulatory requirements published around the world. Moreover, cost of implementing accessibility increases project cost due to manual intervention and dependency on niche skills, which is scarce in industry. Embodiments of the present disclosure provide system and method for automated identification of applicable accessibility guidelines and determination of remediation techniques for fixing issues in webpages, wherein webpages are rendered, and applicable accessibility guidelines are identified based on user interface elements (UI) comprised in the webpages. Further, content associated with rendered webpages are analyzed using the applicable accessibility applicable guidelines to identify webpage non-compliance issue(s) and remediation technique(s) thereof.

Abstract: Accessibility in software engineering is treated as expensive, time consuming and hence adoption of accessibility, is a challenge despite stringent timelines and regulatory requirements published around the world. Moreover, cost of implementing accessibility increases project cost due to manual intervention and dependency on niche skills, which is scarce in industry. Embodiments of the present disclosure provide system and method for automated identification of applicable accessibility guidelines and determination of remediation techniques for fixing issues in webpages, wherein webpages are rendered, and applicable accessibility guidelines are identified based on user interface elements (UI) comprised in the webpages. Further, content associated with rendered webpages are analyzed using the applicable accessibility applicable guidelines to identify webpage non-compliance issue(s) and remediation technique(s) thereof.

Abstract: In spite of complying with accessibility standards and guidelines, it is noted that persons with disabilities (PwD) continue to face usability challenges when accessing content. The present disclosure addresses these challenges by firstly identifying design considerations for each type of disability and facilitates intelligent generation of inclusive system designs that addresses usability and accessibility challenges based on persona, scenario and modality associated with users of all abilities, hence being inclusive. Systems and methods of the present disclosure aide designers with a comprehensive knowledge bank of captured challenges, needs and effectiveness of modalities, the outcomes and existing design considerations that may be prompted at appropriate state of development of system designs to help designers make informed design choices without curtailing their creativity thus digitizing the end-to-end design process.

Abstract: The present disclosure relates to systems and methods for providing inclusive CAPTCHA. The method, in response to a user request for a webpage having CAPTCHA, creates a media file in real-time, wherein the created media file is characterized by distortion interference and corresponds to a selected theme from a plurality of themes associated with real-world scenarios. Further, randomly selecting a comprehension question from a plurality of comprehension questions for the created media file as the CAPTCHA, the comprehension question being based on the selected theme, geography associated with a user requesting the webpage and context of the created media file and transmits the webpage including the CAPTCHA. Further, in response to a user input to the comprehension question, intelligently detecting either a human input or a machine input based on a self-learning CAPTCHA decision module, by considering one or more of spelling errors, incomplete responses, contextual metonyms, synonyms and variants thereof.

Abstract: In spite of complying with accessibility standards and guidelines, it is noted that persons with disabilities (PwD) continue to face usability challenges when accessing content. The present disclosure addresses these challenges by firstly identifying design considerations for each type of disability and facilitates intelligent generation of inclusive system designs that addresses usability and accessibility challenges based on persona, scenario and modality associated with users of all abilities, hence being inclusive. Systems and methods of the present disclosure aide designers with a comprehensive knowledge bank of captured challenges, needs and effectiveness of modalities, the outcomes and existing design considerations that may be prompted at appropriate state of development of system designs to help designers make informed design choices without curtailing their creativity thus digitizing the end-to-end design process.

Abstract: The present disclosure aims to provide CAPTCHA that meets orthogonal requirements of accessibility, usability and security requirements for users of all abilities to make it practically inclusive. The present disclosure provides CAPTCHA questions based on media files associated with real-world scenario thereby ensuring usability and accessibility. Distortion interference is introduced in the media files to ensure security. The questions relate to a selected theme from a plurality of themes. Each theme is further associated with a plurality of media files based on environment and contextual information. Geographical considerations like language and culture are also taken into account to increase usability. The vast repository of media files, types and combinations add to the security aspect of the CAPTCHA.

Abstract: System and method for accessibility testing of a web application is disclosed. Initially the system is configured to receive an accessibility standard and a level of conformance to be achieved for accessibility testing of a webpage associated with the web application. The system is further configured to identify a first set of an accessibility guidelines based on the accessibility standard and the level of conformance. The system further identifies a set of elements present in the webpage and determines a second set of the accessibility guidelines based upon the set of elements and a set of common guidelines applicable to all the webpage's of the web application. Furthermore, the system computes a number of occurrences of each element from the set of elements present in the webpage.

Abstract: System and method for accessibility testing of a web application is disclosed. Initially the system is configured to receive an accessibility standard and a level of conformance to be achieved for accessibility testing of a webpage associated with the web application. The system is further configured to identify a first set of an accessibility guidelines based on the accessibility standard and the level of conformance. The system further identifies a set of elements present in the webpage and determines a second set of the accessibility guidelines based upon the set of elements and a set of common guidelines applicable to all the webpage's of the web application. Furthermore, the system computes a number of occurrences of each element from the set of elements present in the webpage.

Abstract: A scheme for accessing a control register bus and control registers of a microprocessor through a test access port which is configured to an established testing standard. A test access port (TAP) of a microprocessor is configured to communicate serially based on a technique specified in the IEEE 1149.1 standard. External serial instructions are converted for parallel transfer to provide control signals for accessing the internal structures. Serial address and data signals are also converted for parallel transfer to access internal structures on a control register bus and parallel outputs are converted to serial format for external output. By permitting external access to low level internal bus architecture, system testing and debug can be performed by utilizing external programming.

Abstract: A dynamically configurable arrangement for determining performance of a microprocessor. A plurality of functional units in a microprocessor are coupled to a performance counter, wherein the performance counter is incremented in response to occurrence of a predetermined event. A plurality of repeaters coupled between the plurality of functional units and the performance counter. Control circuitry coupled to the plurality of repeaters, wherein the control circuitry selectively enables the repeaters such that only one functional unit is coupled to the performance counter at a particular time.

Abstract: A data processing apparatus having a bidirectional bus circuit is provided. The data processing apparatus further includes a central logic unit and a plurality of peripheral logic units. The bidirectional bus circuit includes a plurality of bus lines for coupling the central logic unit to the peripheral logic units. Moreover, the bidirectional bus circuit includes a plurality of bidirectional data repeaters. Each of the repeaters have a plurality of data ports, wherein one of the ports is coupled to one peripheral logic unit cluster. The bidirectional data repeaters further include peripheral branch identification circuits for receiving a peripheral identification signal from the central logic unit and for generating a directioning signal responsive to the peripheral identification signal.

Abstract: A system for filtering multiple event signals from multiple event-generating sources. A selection circuit receives the multiple event signals and selects one of the event signals. A filter circuit is coupled to the selection circuit and receives the selected event signal from the selection circuit. The filter circuit produces a filtered event signal. A counter receives the filtered event signal from the filter circuit and is incremented in response to the filtered event signal. The filter circuit includes a comparison logic circuit and an edge detection logic circuit.

Abstract: A carry-skip incrementor mitigating propagation delay experienced by conventional ripple carry incrementors without employing a substantially greater device count, includes a plurality of circuit blocks operating in combination with a plurality of logic gates. Each circuit block receives as input a varying number of data bits of an input operand and a carry signal and thereafter, generates a product signal and real bit sums corresponding to these data bits. The plurality of logic gates are arranged such that each logic gate receives as input the product signal from a first adjacent circuit block and the carry signal and outputs the carry signal for a second adjacent circuit block. The carry signal is active if the product signal and the carry signal are active. Thus, the delay associated with the first adjacent circuit block is bypassed in favor of the delay associated with the logic gate.