Patents by Inventor Sumeet Bhagavat

Sumeet Bhagavat has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240125003
    Abstract: A method of growing a single crystal ingot includes growing a single crystal silicon ingot from a silicon melt in a crucible within an inner chamber, adding a volatile dopant into a feed tube, positioning the feed tube within an inner chamber at a first height relative to a surface of the melt, adjusting the feed tube within the inner chamber to a second height at a speed rate, and heating the volatile dopant to form a gaseous dopant as the feed tube is moved from the first height to the second height at the speed rate. Each of the second height and the speed rate are selected to control a vaporization rate of the volatile dopant. The method also includes introducing dopant species into the melt while growing the ingot by contacting the surface of the melt with the gaseous dopant.
    Type: Application
    Filed: October 13, 2022
    Publication date: April 18, 2024
    Inventors: Chieh HU, Hsien-Ta TSENG, Chun-Sheng WU, William Lynn LUTER, Liang-Chin CHEN, Sumeet BHAGAVAT, Carissima Marie HUDSON, Yu-Chiao Wu
  • Publication number: 20240125004
    Abstract: A method of growing a single crystal ingot includes growing a single crystal silicon ingot from a silicon melt in a crucible within an inner chamber, adding a volatile dopant into a feed tube, positioning the feed tube within an inner chamber at a first height relative to a surface of the melt, adjusting the feed tube within the inner chamber to a second height at a speed rate, and heating the volatile dopant to form a gaseous dopant as the feed tube is moved from the first height to the second height at the speed rate. Each of the second height and the speed rate are selected to control a vaporization rate of the volatile dopant. The method also includes introducing dopant species into the melt while growing the ingot by contacting the surface of the melt with the gaseous dopant.
    Type: Application
    Filed: October 13, 2022
    Publication date: April 18, 2024
    Inventors: Chieh HU, Hsien-Ta TSENG, Chun-Sheng WU, William Lynn LUTER, Liang-Chin CHEN, Sumeet BHAGAVAT, Carissima Marie HUDSON, Yu-Chiao Wu
  • Publication number: 20230250551
    Abstract: A method for producing a silicon ingot includes withdrawing a seed crystal from a melt that includes melted silicon in a crucible that is enclosed in a vacuum chamber containing a cusped magnetic field. At least one process parameter is regulated in at least two stages, including a first stage corresponding to formation of the silicon ingot up to an intermediate ingot length, and a second stage corresponding to formation of the silicon ingot from the intermediate ingot length to the total ingot length. During the second stage process parameter regulation may include reducing a crystal rotation rate, reducing a crucible rotation rate, and/or increasing a magnetic field strength relative to the first stage.
    Type: Application
    Filed: April 11, 2023
    Publication date: August 10, 2023
    Inventors: Gaurab Samanta, Parthiv Daggolu, Sumeet Bhagavat, Soubir Basak, Nan Zhang
  • Patent number: 11668020
    Abstract: A method for producing a silicon ingot includes withdrawing a seed crystal from a melt that includes melted silicon in a crucible that is enclosed in a vacuum chamber containing a cusped magnetic field. At least one process parameter is regulated in at least two stages, including a first stage corresponding to formation of the silicon ingot up to an intermediate ingot length, and a second stage corresponding to formation of the silicon ingot from the intermediate ingot length to the total ingot length. During the second stage process parameter regulation may include reducing a crystal rotation rate, reducing a crucible rotation rate, and/or increasing a magnetic field strength relative to the first stage.
    Type: Grant
    Filed: July 20, 2021
    Date of Patent: June 6, 2023
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Gaurab Samanta, Parthiv Daggolu, Sumeet Bhagavat, Soubir Basak, Nan Zhang
  • Publication number: 20210348298
    Abstract: A method for producing a silicon ingot includes withdrawing a seed crystal from a melt that includes melted silicon in a crucible that is enclosed in a vacuum chamber containing a cusped magnetic field. At least one process parameter is regulated in at least two stages, including a first stage corresponding to formation of the silicon ingot up to an intermediate ingot length, and a second stage corresponding to formation of the silicon ingot from the intermediate ingot length to the total ingot length. During the second stage process parameter regulation may include reducing a crystal rotation rate, reducing a crucible rotation rate, and/or increasing a magnetic field strength relative to the first stage.
    Type: Application
    Filed: July 20, 2021
    Publication date: November 11, 2021
    Inventors: Gaurab Samanta, Parthiv Daggolu, Sumeet Bhagavat, Soubir Basak, Nan Zhang
  • Patent number: 11136691
    Abstract: A method for producing a silicon ingot includes withdrawing a seed crystal from a melt that includes melted silicon in a crucible that is enclosed in a vacuum chamber containing a cusped magnetic field. At least one process parameter is regulated in at least two stages, including a first stage corresponding to formation of the silicon ingot up to an intermediate ingot length, and a second stage corresponding to formation of the silicon ingot from the intermediate ingot length to the total ingot length. During the second stage process parameter regulation may include reducing a crystal rotation rate, reducing a crucible rotation rate, and/or increasing a magnetic field strength relative to the first stage.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: October 5, 2021
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Gaurab Samanta, Parthiv Daggolu, Sumeet Bhagavat, Soubir Basak, Nan Zhang
  • Patent number: 11081359
    Abstract: Methods for polishing semiconductor substrates that involve adjusting the finish polishing sequence based on the pad-to-pad variance of the polishing pad are disclosed.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: August 3, 2021
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Ichiro Yoshimura, Alex Chu, H. J. Chiu, Sumeet Bhagavat, TaeHyeong Kim, Norimasa Katakura, Masaru Kitazawa
  • Publication number: 20200392643
    Abstract: A method for producing a silicon ingot includes withdrawing a seed crystal from a melt that includes melted silicon in a crucible that is enclosed in a vacuum chamber containing a cusped magnetic field. At least one process parameter is regulated in at least two stages, including a first stage corresponding to formation of the silicon ingot up to an intermediate ingot length, and a second stage corresponding to formation of the silicon ingot from the intermediate ingot length to the total ingot length. During the second stage process parameter regulation may include reducing a crystal rotation rate, reducing a crucible rotation rate, and/or increasing a magnetic field strength relative to the first stage.
    Type: Application
    Filed: June 30, 2020
    Publication date: December 17, 2020
    Inventors: Gaurab Samanta, Parthiv Daggolu, Sumeet Bhagavat, Soubir Basak, Nan Zhang
  • Patent number: 10745823
    Abstract: A method for producing a silicon ingot includes withdrawing a seed crystal from a melt that includes melted silicon in a crucible that is enclosed in a vacuum chamber containing a cusped magnetic field. At least one process parameter is regulated in at least two stages, including a first stage corresponding to formation of the silicon ingot up to an intermediate ingot length, and a second stage corresponding to formation of the silicon ingot from the intermediate ingot length to the total ingot length. During the second stage process parameter regulation may include reducing a crystal rotation rate, reducing a crucible rotation rate, and/or increasing a magnetic field strength relative to the first stage.
    Type: Grant
    Filed: December 1, 2016
    Date of Patent: August 18, 2020
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Gaurab Samanta, Parthiv Daggolu, Sumeet Bhagavat, Soubir Basak, Nan Zhang
  • Publication number: 20200083057
    Abstract: Methods for polishing semiconductor substrates that involve adjusting the finish polishing sequence based on the pad-to-pad variance of the polishing pad are disclosed.
    Type: Application
    Filed: August 22, 2019
    Publication date: March 12, 2020
    Inventors: Ichiro Yoshimura, Alex Chu, H.J. Chiu, Sumeet Bhagavat, TaeHyeong Kim, Norimasa Katakura, Masaru Kitazawa
  • Publication number: 20180355509
    Abstract: A method for producing a silicon ingot includes withdrawing a seed crystal from a melt that includes melted silicon in a crucible that is enclosed in a vacuum chamber containing a cusped magnetic field. At least one process parameter is regulated in at least two stages, including a first stage corresponding to formation of the silicon ingot up to an intermediate ingot length, and a second stage corresponding to formation of the silicon ingot from the intermediate ingot length to the total ingot length. During the second stage process parameter regulation may include reducing a crystal rotation rate, reducing a crucible rotation rate, and/or increasing a magnetic field strength relative to the first stage.
    Type: Application
    Filed: December 1, 2016
    Publication date: December 13, 2018
    Inventors: Gaurab Samanta, Parthiv Daggolu, Sumeet Bhagavat, Soubir Basak, Nan Zhang
  • Patent number: 9566687
    Abstract: A polishing head assembly for single side polishing of silicon wafers is provided. The polishing head assembly includes a polishing head and a cap. The polishing head has a recess along a bottom portion, the recess having a recessed surface. The cap is positioned within the recess, and has an annular wall and a floor extending across the annular wall. The floor is spaced from the recessed surface to form a chamber therebetween. The chamber is configured to be pressurized for deflecting the floor. The annular wall is attached to the polishing head with an adhesive.
    Type: Grant
    Filed: October 13, 2014
    Date of Patent: February 14, 2017
    Assignee: SunEdison Semiconductor Limited (UEN201334164H)
    Inventors: Peter Albrecht, Sumeet Bhagavat, Alex Chu, Ichiro Yoshimura, Yunbiao Xin, Roland Vandamme
  • Publication number: 20160101502
    Abstract: A polishing head assembly for single side polishing of silicon wafers is provided. The polishing head assembly includes a polishing head and a cap. The polishing head has a recess along a bottom portion, the recess having a recessed surface. The cap is positioned within the recess, and has an annular wall and a floor extending across the annular wall. The floor is spaced from the recessed surface to form a chamber therebetween. The chamber is configured to be pressurized for deflecting the floor. The annular wall is attached to the polishing head with an adhesive.
    Type: Application
    Filed: October 13, 2014
    Publication date: April 14, 2016
    Inventors: Peter Albrecht, Sumeet Bhagavat, Alex Chu, Ichiro Yoshimura, Yunbiao Xin, Roland Vandamme
  • Publication number: 20140357161
    Abstract: A polishing head assembly for single side polishing of silicon wafers includes a polishing head and a cap. The polishing head includes a top surface and a bottom surface and defines a longitudinal axis extending therethrough. The cap is positioned coaxially with the polishing head and includes an upper surface and a lower surface. The upper surface is spaced from the bottom surface of the polishing head to form a chamber that allows the cap to deflect toward the polishing head.
    Type: Application
    Filed: May 31, 2014
    Publication date: December 4, 2014
    Inventors: Sumeet Bhagavat, Peter Albrecht, Alex Chu, Ichiro Yoshimura, Yunbiao Xin, Roland Vandamme
  • Publication number: 20070179660
    Abstract: A double side grinder comprises a pair of grinding wheels and a pair of hydrostatic pads operable to hold a flat workpiece (e.g., semiconductor wafer) so that part of the workpiece is positioned between the grinding wheels and part of the workpiece is positioned between the hydrostatic pads. At least one sensor measures a distance between the workpiece and the respective sensor for assessing nanotopology of the workpiece. In a method of the invention, a distance to the workpiece is measured during grinding and used to assess nanotopology of the workpiece. For instance, a finite element structural analysis of the workpiece can be performed using sensor data to derive at least one boundary condition. The nanotopology assessment can begin before the workpiece is removed from the grinder, providing rapid nanotopology feedback. A spatial filter can be used to predict the likely nanotopology of the workpiece after further processing.
    Type: Application
    Filed: December 28, 2006
    Publication date: August 2, 2007
    Applicant: MEMC ELECTRONIC MATERIALS, INC.
    Inventors: Sumeet Bhagavat, Milind Bhagavat, Roland Vandamme, Tomomi Komura