Patents by Inventor Sumeet Bhagavat
Sumeet Bhagavat has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240125003Abstract: A method of growing a single crystal ingot includes growing a single crystal silicon ingot from a silicon melt in a crucible within an inner chamber, adding a volatile dopant into a feed tube, positioning the feed tube within an inner chamber at a first height relative to a surface of the melt, adjusting the feed tube within the inner chamber to a second height at a speed rate, and heating the volatile dopant to form a gaseous dopant as the feed tube is moved from the first height to the second height at the speed rate. Each of the second height and the speed rate are selected to control a vaporization rate of the volatile dopant. The method also includes introducing dopant species into the melt while growing the ingot by contacting the surface of the melt with the gaseous dopant.Type: ApplicationFiled: October 13, 2022Publication date: April 18, 2024Inventors: Chieh HU, Hsien-Ta TSENG, Chun-Sheng WU, William Lynn LUTER, Liang-Chin CHEN, Sumeet BHAGAVAT, Carissima Marie HUDSON, Yu-Chiao Wu
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Publication number: 20240125004Abstract: A method of growing a single crystal ingot includes growing a single crystal silicon ingot from a silicon melt in a crucible within an inner chamber, adding a volatile dopant into a feed tube, positioning the feed tube within an inner chamber at a first height relative to a surface of the melt, adjusting the feed tube within the inner chamber to a second height at a speed rate, and heating the volatile dopant to form a gaseous dopant as the feed tube is moved from the first height to the second height at the speed rate. Each of the second height and the speed rate are selected to control a vaporization rate of the volatile dopant. The method also includes introducing dopant species into the melt while growing the ingot by contacting the surface of the melt with the gaseous dopant.Type: ApplicationFiled: October 13, 2022Publication date: April 18, 2024Inventors: Chieh HU, Hsien-Ta TSENG, Chun-Sheng WU, William Lynn LUTER, Liang-Chin CHEN, Sumeet BHAGAVAT, Carissima Marie HUDSON, Yu-Chiao Wu
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Publication number: 20230250551Abstract: A method for producing a silicon ingot includes withdrawing a seed crystal from a melt that includes melted silicon in a crucible that is enclosed in a vacuum chamber containing a cusped magnetic field. At least one process parameter is regulated in at least two stages, including a first stage corresponding to formation of the silicon ingot up to an intermediate ingot length, and a second stage corresponding to formation of the silicon ingot from the intermediate ingot length to the total ingot length. During the second stage process parameter regulation may include reducing a crystal rotation rate, reducing a crucible rotation rate, and/or increasing a magnetic field strength relative to the first stage.Type: ApplicationFiled: April 11, 2023Publication date: August 10, 2023Inventors: Gaurab Samanta, Parthiv Daggolu, Sumeet Bhagavat, Soubir Basak, Nan Zhang
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Patent number: 11668020Abstract: A method for producing a silicon ingot includes withdrawing a seed crystal from a melt that includes melted silicon in a crucible that is enclosed in a vacuum chamber containing a cusped magnetic field. At least one process parameter is regulated in at least two stages, including a first stage corresponding to formation of the silicon ingot up to an intermediate ingot length, and a second stage corresponding to formation of the silicon ingot from the intermediate ingot length to the total ingot length. During the second stage process parameter regulation may include reducing a crystal rotation rate, reducing a crucible rotation rate, and/or increasing a magnetic field strength relative to the first stage.Type: GrantFiled: July 20, 2021Date of Patent: June 6, 2023Assignee: GlobalWafers Co., Ltd.Inventors: Gaurab Samanta, Parthiv Daggolu, Sumeet Bhagavat, Soubir Basak, Nan Zhang
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Publication number: 20210348298Abstract: A method for producing a silicon ingot includes withdrawing a seed crystal from a melt that includes melted silicon in a crucible that is enclosed in a vacuum chamber containing a cusped magnetic field. At least one process parameter is regulated in at least two stages, including a first stage corresponding to formation of the silicon ingot up to an intermediate ingot length, and a second stage corresponding to formation of the silicon ingot from the intermediate ingot length to the total ingot length. During the second stage process parameter regulation may include reducing a crystal rotation rate, reducing a crucible rotation rate, and/or increasing a magnetic field strength relative to the first stage.Type: ApplicationFiled: July 20, 2021Publication date: November 11, 2021Inventors: Gaurab Samanta, Parthiv Daggolu, Sumeet Bhagavat, Soubir Basak, Nan Zhang
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Patent number: 11136691Abstract: A method for producing a silicon ingot includes withdrawing a seed crystal from a melt that includes melted silicon in a crucible that is enclosed in a vacuum chamber containing a cusped magnetic field. At least one process parameter is regulated in at least two stages, including a first stage corresponding to formation of the silicon ingot up to an intermediate ingot length, and a second stage corresponding to formation of the silicon ingot from the intermediate ingot length to the total ingot length. During the second stage process parameter regulation may include reducing a crystal rotation rate, reducing a crucible rotation rate, and/or increasing a magnetic field strength relative to the first stage.Type: GrantFiled: June 30, 2020Date of Patent: October 5, 2021Assignee: GlobalWafers Co., Ltd.Inventors: Gaurab Samanta, Parthiv Daggolu, Sumeet Bhagavat, Soubir Basak, Nan Zhang
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Patent number: 11081359Abstract: Methods for polishing semiconductor substrates that involve adjusting the finish polishing sequence based on the pad-to-pad variance of the polishing pad are disclosed.Type: GrantFiled: August 22, 2019Date of Patent: August 3, 2021Assignee: GlobalWafers Co., Ltd.Inventors: Ichiro Yoshimura, Alex Chu, H. J. Chiu, Sumeet Bhagavat, TaeHyeong Kim, Norimasa Katakura, Masaru Kitazawa
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Publication number: 20200392643Abstract: A method for producing a silicon ingot includes withdrawing a seed crystal from a melt that includes melted silicon in a crucible that is enclosed in a vacuum chamber containing a cusped magnetic field. At least one process parameter is regulated in at least two stages, including a first stage corresponding to formation of the silicon ingot up to an intermediate ingot length, and a second stage corresponding to formation of the silicon ingot from the intermediate ingot length to the total ingot length. During the second stage process parameter regulation may include reducing a crystal rotation rate, reducing a crucible rotation rate, and/or increasing a magnetic field strength relative to the first stage.Type: ApplicationFiled: June 30, 2020Publication date: December 17, 2020Inventors: Gaurab Samanta, Parthiv Daggolu, Sumeet Bhagavat, Soubir Basak, Nan Zhang
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Patent number: 10745823Abstract: A method for producing a silicon ingot includes withdrawing a seed crystal from a melt that includes melted silicon in a crucible that is enclosed in a vacuum chamber containing a cusped magnetic field. At least one process parameter is regulated in at least two stages, including a first stage corresponding to formation of the silicon ingot up to an intermediate ingot length, and a second stage corresponding to formation of the silicon ingot from the intermediate ingot length to the total ingot length. During the second stage process parameter regulation may include reducing a crystal rotation rate, reducing a crucible rotation rate, and/or increasing a magnetic field strength relative to the first stage.Type: GrantFiled: December 1, 2016Date of Patent: August 18, 2020Assignee: GlobalWafers Co., Ltd.Inventors: Gaurab Samanta, Parthiv Daggolu, Sumeet Bhagavat, Soubir Basak, Nan Zhang
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Publication number: 20200083057Abstract: Methods for polishing semiconductor substrates that involve adjusting the finish polishing sequence based on the pad-to-pad variance of the polishing pad are disclosed.Type: ApplicationFiled: August 22, 2019Publication date: March 12, 2020Inventors: Ichiro Yoshimura, Alex Chu, H.J. Chiu, Sumeet Bhagavat, TaeHyeong Kim, Norimasa Katakura, Masaru Kitazawa
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Publication number: 20180355509Abstract: A method for producing a silicon ingot includes withdrawing a seed crystal from a melt that includes melted silicon in a crucible that is enclosed in a vacuum chamber containing a cusped magnetic field. At least one process parameter is regulated in at least two stages, including a first stage corresponding to formation of the silicon ingot up to an intermediate ingot length, and a second stage corresponding to formation of the silicon ingot from the intermediate ingot length to the total ingot length. During the second stage process parameter regulation may include reducing a crystal rotation rate, reducing a crucible rotation rate, and/or increasing a magnetic field strength relative to the first stage.Type: ApplicationFiled: December 1, 2016Publication date: December 13, 2018Inventors: Gaurab Samanta, Parthiv Daggolu, Sumeet Bhagavat, Soubir Basak, Nan Zhang
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Patent number: 9566687Abstract: A polishing head assembly for single side polishing of silicon wafers is provided. The polishing head assembly includes a polishing head and a cap. The polishing head has a recess along a bottom portion, the recess having a recessed surface. The cap is positioned within the recess, and has an annular wall and a floor extending across the annular wall. The floor is spaced from the recessed surface to form a chamber therebetween. The chamber is configured to be pressurized for deflecting the floor. The annular wall is attached to the polishing head with an adhesive.Type: GrantFiled: October 13, 2014Date of Patent: February 14, 2017Assignee: SunEdison Semiconductor Limited (UEN201334164H)Inventors: Peter Albrecht, Sumeet Bhagavat, Alex Chu, Ichiro Yoshimura, Yunbiao Xin, Roland Vandamme
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Publication number: 20160101502Abstract: A polishing head assembly for single side polishing of silicon wafers is provided. The polishing head assembly includes a polishing head and a cap. The polishing head has a recess along a bottom portion, the recess having a recessed surface. The cap is positioned within the recess, and has an annular wall and a floor extending across the annular wall. The floor is spaced from the recessed surface to form a chamber therebetween. The chamber is configured to be pressurized for deflecting the floor. The annular wall is attached to the polishing head with an adhesive.Type: ApplicationFiled: October 13, 2014Publication date: April 14, 2016Inventors: Peter Albrecht, Sumeet Bhagavat, Alex Chu, Ichiro Yoshimura, Yunbiao Xin, Roland Vandamme
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Publication number: 20140357161Abstract: A polishing head assembly for single side polishing of silicon wafers includes a polishing head and a cap. The polishing head includes a top surface and a bottom surface and defines a longitudinal axis extending therethrough. The cap is positioned coaxially with the polishing head and includes an upper surface and a lower surface. The upper surface is spaced from the bottom surface of the polishing head to form a chamber that allows the cap to deflect toward the polishing head.Type: ApplicationFiled: May 31, 2014Publication date: December 4, 2014Inventors: Sumeet Bhagavat, Peter Albrecht, Alex Chu, Ichiro Yoshimura, Yunbiao Xin, Roland Vandamme
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Publication number: 20070179660Abstract: A double side grinder comprises a pair of grinding wheels and a pair of hydrostatic pads operable to hold a flat workpiece (e.g., semiconductor wafer) so that part of the workpiece is positioned between the grinding wheels and part of the workpiece is positioned between the hydrostatic pads. At least one sensor measures a distance between the workpiece and the respective sensor for assessing nanotopology of the workpiece. In a method of the invention, a distance to the workpiece is measured during grinding and used to assess nanotopology of the workpiece. For instance, a finite element structural analysis of the workpiece can be performed using sensor data to derive at least one boundary condition. The nanotopology assessment can begin before the workpiece is removed from the grinder, providing rapid nanotopology feedback. A spatial filter can be used to predict the likely nanotopology of the workpiece after further processing.Type: ApplicationFiled: December 28, 2006Publication date: August 2, 2007Applicant: MEMC ELECTRONIC MATERIALS, INC.Inventors: Sumeet Bhagavat, Milind Bhagavat, Roland Vandamme, Tomomi Komura