Patents by Inventor Sumeet Gupta

Sumeet Gupta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12212635
    Abstract: A method of traffic forwarding and disambiguation through the use of local proxies and addresses. The technique leverages DNS to on-ramp traffic to a local proxy. The local proxy runs on the end user's device. According to a first embodiment, DNS is used to remap what would normally be a wide range of IP addresses to localhost based on 127.0.0.0/8 listening sockets, where the system can then listen for connections and data. In a second embodiment, a localhost proxy based on a TUN/TAP interface (or other packet interception method) with a user-defined CIDR range to which the local DNS server drives traffic is used. Requests on that local proxy are annotated (by adding data to the upstream connection).
    Type: Grant
    Filed: January 3, 2023
    Date of Patent: January 28, 2025
    Assignee: Akamai Technologies, Inc.
    Inventors: Seetharama Sarma Ayyadevara, Charles E. Gero, Stephan Benny, Pravin Tatti, Manoj Kumar, Seemant Choudhary, Robert Lauro Quiros, Priyatham Phani Srinath Adigopula, Poornima Venkatesha, Sumeet Gupta
  • Publication number: 20240283436
    Abstract: A serial data receiver subsystem of a computer system includes a data rate detection circuit and a receiver circuit. The data rate detection circuit is configured to detect that a communication link operates in a high-speed mode rather than in a low-speed mode by detecting that a number of transitions in a serial data stream over a reference period of time exceeds a threshold value. The date rate detection circuit is further configured to activate a data rate detection signal indicating that the communication link operates in the high-speed mode, the data rate detection signal activated in response to detection that the number of transitions in the serial data stream over the reference period of time exceeds the threshold value. The receiver circuit is configured to activate one or more of a plurality of subcircuits included in the receiver circuit in response to activation of the data rate detection signal.
    Type: Application
    Filed: April 26, 2024
    Publication date: August 22, 2024
    Inventors: Vishal Varma, Dhaval H. Shah, Jose A. Tierno, Sanjeev K. Maheshwari, Sumeet Gupta
  • Patent number: 12028075
    Abstract: A serial data receiver subsystem included in a computer system may include a data detection circuit, a speed detection circuit, and a receiver circuit that includes multiple subcircuits. The data detection circuit performs a comparison of a reference voltage to the magnitude of signals received via a communication link that encodes a serial data stream consisting of multiple data symbols. Using a result of the comparison, the data detection circuit may activate a signal present indicator indicating the presence of data on the communication link. Once the signal present indicator is active, the speed detection circuit checks the number of transitions to determine a rate at which data is being transmitted. In response to a determination that the rate of the data being transmitted exceeds a threshold value, the receiver circuit activates one or more of the multiple subcircuits.
    Type: Grant
    Filed: August 31, 2022
    Date of Patent: July 2, 2024
    Assignee: Apple Inc.
    Inventors: Vishal Varma, Dhaval H. Shah, Jose A. Tierno, Sanjeev K. Maheshwari, Sumeet Gupta
  • Publication number: 20230387898
    Abstract: A serial data receiver subsystem included in a computer system may include a data detection circuit, a speed detection circuit, and a receiver circuit that includes multiple subcircuits. The data detection circuit performs a comparison a reference voltage to the magnitude of signals received via a communication link that encode a serial data stream consisting of multiple data symbols. Using a result of the comparison, the data detection circuit may activate a indicating the presence of data on the communication link. Once the is active, the speed detection circuit checks the number of transitions to determine a rate at which data is being transmitted. In response to a determination that the rate of the data being transmitted exceeds a threshold value, the receiver circuit activates one or more of the multiple subcircuits.
    Type: Application
    Filed: August 31, 2022
    Publication date: November 30, 2023
    Inventors: Vishal Varma, Dhaval H. Shah, Jose A. Tierno, Sanjeev K. Maheshwari, Sumeet Gupta
  • Publication number: 20230133809
    Abstract: A method of traffic forwarding and disambiguation through the use of local proxies and addresses. The technique leverages DNS to on-ramp traffic to a local proxy. The local proxy runs on the end user's device. According to a first embodiment, DNS is used to remap what would normally be a wide range of IP addresses to localhost based on 127.0.0.0/8 listening sockets, where the system can then listen for connections and data. In a second embodiment, a localhost proxy based on a TUN/TAP interface (or other packet interception method) with a user-defined CIDR range to which the local DNS server drives traffic is used. Requests on that local proxy are annotated (by adding data to the upstream connection).
    Type: Application
    Filed: January 3, 2023
    Publication date: May 4, 2023
    Applicant: Akamai Technologies, Inc.
    Inventors: Seetharama Sarma Ayyadevara, Charles E. Gero, Stephan Benny, Pravin Tatti, Manoj Kumar, Seemant Choudhary, Robert Lauro Quiros, Priyatham Phani Srinath Adigopula, Poornima Venkatesha, Sr., Sumeet Gupta
  • Patent number: 11546444
    Abstract: A method of traffic forwarding and disambiguation through the use of local proxies and addresses. The technique leverages DNS to on-ramp traffic to a local proxy. The local proxy runs on the end user's device. According to a first embodiment, DNS is used to remap what would normally be a wide range of IP addresses to localhost based on 127.0.0.0/8 listening sockets, where the system can then listen for connections and data. In a second embodiment, a localhost proxy based on a TUN/TAP interface (or other packet interception method) with a user-defined CIDR range to which the local DNS server drives traffic is used. Requests on that local proxy are annotated (by adding data to the upstream connection).
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: January 3, 2023
    Assignee: Akamai Technologies, Inc.
    Inventors: Seetharama Sarma Ayyadevara, Charles E. Gero, Stephan Benny, Pravin Tatti, Manoj Kumar, Seemant Choudhary, Robert Lauro Quiros, Priyatham Phani Srinath Adigopula, Poornima Venkatesha, Sr., Sumeet Gupta
  • Patent number: 11101673
    Abstract: Techniques for control of power switches in a USB Power Delivery (USB-PD) system are described herein. In an example embodiment, an integrated circuit comprises a programmable gate control circuit coupled to a provider field effect transistor (FET) and a consumer FET to provide control signals to the provider and consumer FETs in response to system conditions and application requirements of the USB-PD system. A pulldown current control circuit may provide additional control to slew rate for the slow turn-ON of provider and consumer FETs.
    Type: Grant
    Filed: May 18, 2018
    Date of Patent: August 24, 2021
    Assignee: Cypress Semiconductor Corporation
    Inventors: Derwin Mattos, Hamid Khodabandehlou, Sumeet Gupta, Syed Raza, Anup Nayak
  • Patent number: 10672475
    Abstract: Embodiments include nonvolatile a memory (NVM) device that can be configured for logic switching and/or digital computing. For example, embodiments of the NVM device can be configured as any one or combination of a memory cell, a D flip flop (DFF), a Backup and Restore circuit (B&R circuit), and/or a latch for a DFF. Any of the NVM devices can have a Fe field effect transistors (FeFET) configured to exploit the IDS?VG hysteresis of the steep switch at low voltage for logic memory synergy. The FeFET-based devices can be configured to include a wide hysteresis, a steep hysteresis edge, and high ratio between the two IDS states at VG=0.
    Type: Grant
    Filed: September 24, 2019
    Date of Patent: June 2, 2020
    Assignee: The Penn State Research Foundation
    Inventors: Xueqing Li, Sumitha George, John Sampson, Sumeet Gupta, Suman Datta, Vijaykrishnan Narayanan, Kaisheng Ma
  • Patent number: 10645129
    Abstract: Disclosed are various embodiments for correlating the measured engagement of attendees to an online conference with the content of the online conference. In one implementation, a timeline is displayed in a user interface for at least a portion of the online conference. The timeline correlates the engagement of the attendees with the content of the online conference based on compiling values measured for engagement parameters of the respective attendees at defined time intervals during the online conference. Input is received identifying a point or interval of the timeline of the online conference. In response to receiving the input, content of the online conference associated with the point or interval is identified and displayed. Alternatively or in addition to displaying content, multiple, different ones of the engagement parameters for the point or interval are identified and have the respective values displayed.
    Type: Grant
    Filed: March 3, 2015
    Date of Patent: May 5, 2020
    Assignee: Adobe Inc.
    Inventors: Anurag Aggarwal, Ajay Jain, Sumeet Gupta, Mili Sharma
  • Patent number: 10599597
    Abstract: Techniques for voltage discharge from a USB Power Delivery (USB-PD) VBUS line are described herein. In an example embodiment, an integrated circuit comprises a discharge control logic coupled to a first discharge circuit and to a second discharge circuit. The first discharge circuit configured to couple to a power source node on the VBUS line. The second discharge circuit configured to couple to an output node on the VBUS line. The discharge control logic is configured to independently control the first discharge circuit and the second discharge circuit to discharge the voltage on the VBUS line.
    Type: Grant
    Filed: May 18, 2018
    Date of Patent: March 24, 2020
    Assignee: Cypress Semiconductor Corporation
    Inventors: Derwin Mattos, Godwin Gerald Arulappan, Syed Raza, Anup Nayak, Sumeet Gupta, Venkat Mandagulathur
  • Publication number: 20200027508
    Abstract: Embodiments include nonvolatile a memory (NVM) device that can be configured for logic switching and/or digital computing. For example, embodiments of the NVM device can be configured as any one or combination of a memory cell, a D flip flop (DFF), a Backup and Restore circuit (B&R circuit), and/or a latch for a DFF. Any of the NVM devices can have a Fe field effect transistors (FeFET) configured to exploit the IDS?VG hysteresis of the steep switch at low voltage for logic memory synergy. The FeFET-based devices can be configured to include a wide hysteresis, a steep hysteresis edge, and high ratio between the two IDS states at VG=0.
    Type: Application
    Filed: September 24, 2019
    Publication date: January 23, 2020
    Inventors: Xueqing Li, Sumitha George, John Sampson, Sumeet Gupta, Suman Datta, Vijaykrishnan Narayanan, Kaisheng Ma
  • Patent number: 10475514
    Abstract: Embodiments include nonvolatile a memory (NVM) device that can be configured for logic switching and/or digital computing. For example, embodiments of the NVM device can be configured as any one or combination of a memory cell, a D flip flop (DFF), a Backup and Restore circuit (B&R circuit), and/or a latch for a DFF. Any of the NVM devices can have a Fe field effect transistors (FeFET) configured to exploit the IDS-VG hysteresis of the steep switch at low voltage for logic memory synergy. The FeFET-based devices can be configured to include a wide hysteresis, a steep hysteresis edge, and high ratio between the two IDS states at VG=0.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: November 12, 2019
    Assignee: The Penn State Research Foundation
    Inventors: Xueqing Li, Sumitha George, John Sampson, Sumeet Gupta, Suman Datta, Vijaykrishnan Narayanan, Kaisheng Ma
  • Publication number: 20190297161
    Abstract: A method of traffic forwarding and disambiguation through the use of local proxies and addresses. The technique leverages DNS to on-ramp traffic to a local proxy. The local proxy runs on the end user's device. According to a first embodiment, DNS is used to remap what would normally be a wide range of IP addresses to localhost based on 127.0.0.0/8 listening sockets, where the system can then listen for connections and data. In a second embodiment, a localhost proxy based on a TUN/TAP interface (or other packet interception method) with a user-defined CIDR range to which the local DNS server drives traffic is used. Requests on that local proxy are annotated (by adding data to the upstream connection).
    Type: Application
    Filed: March 22, 2019
    Publication date: September 26, 2019
    Applicant: Akamai Technologies, Inc.
    Inventors: Seetharama Sarma Ayyadevara, Charles E. Gero, Stephan Benny, Pravin Tatti, Manoj Kumar, Seemant Choudhary, Robert Lauro Quiros, Priyatham Phani Srinath Adigopula, Poornima Venkatesha, SR., Sumeet Gupta
  • Publication number: 20190288532
    Abstract: Techniques for control of power switches in a USB Power Delivery (USB-PD) system are described herein. In an example embodiment, an integrated circuit comprises a programmable gate control circuit coupled to a provider field effect transistor (FET) and a consumer FET to provide control signals to the provider and consumer FETs in response to system conditions and application requirements of the USB-PD system. A pulldown current control circuit may provide additional control to slew rate for the slow turn-ON of provider and consumer FETs.
    Type: Application
    Filed: May 18, 2018
    Publication date: September 19, 2019
    Applicant: Cypress Semiconductor Corporation
    Inventors: Derwin Mattos, Hamid Khodabandehlou, Sumeet Gupta, Syed Raza, Anup Nayak
  • Publication number: 20190278731
    Abstract: Techniques for voltage discharge from a USB Power Delivery (USB-PD) VBUS line are described herein. In an example embodiment, an integrated circuit comprises a discharge control logic coupled to a first discharge circuit and to a second discharge circuit. The first discharge circuit configured to couple to a power source node on the VBUS line. The second discharge circuit configured to couple to an output node on the VBUS line. The discharge control logic is configured to independently control the first discharge circuit and the second discharge circuit to discharge the voltage on the VBUS line.
    Type: Application
    Filed: May 18, 2018
    Publication date: September 12, 2019
    Applicant: Cypress Semiconductor Corporation
    Inventors: Derwin Mattos, Godwin Gerald Arulappan, Syed Raza, Anup Nayak, Sumeet Gupta, Venkat Mandagulathur
  • Publication number: 20180330791
    Abstract: Embodiments include nonvolatile a memory (NVM) device that can be configured for logic switching and/or digital computing. For example, embodiments of the NVM device can be configured as any one or combination of a memory cell, a D flip flop (DFF), a Backup and Restore circuit (B&R circuit), and/or a latch for a DFF. Any of the NVM devices can have a Fe field effect transistors (FeFET) configured to exploit the IDS?VG hysteresis of the steep switch at low voltage for logic memory synergy. The FeFET-based devices can be configured to include a wide hysteresis, a steep hysteresis edge, and high ratio between the two IDS states at VG=0.
    Type: Application
    Filed: May 10, 2018
    Publication date: November 15, 2018
    Inventors: Xueqing Li, Sumitha George, John Sampson, Sumeet Gupta, Suman Datta, Vijaykrishnan Narayanan, Kaisheng Ma
  • Patent number: 9923937
    Abstract: Users can participate in various different types of online sessions, such as webinars, massive open online courses (MOOCs), social learning sessions, and so forth. A record of interactions that the user has with an online session is maintained. During the online session, the user may become disengaged from the online session for various reasons, such as the user losing interest in the information being presented, the user becoming sidetracked due to other programs running on his or her computer or phone, and so forth. The techniques discussed herein detect that a user is not engaged in the online session and generate dynamic content to attempt to re-engage the user in the online session. This dynamic content is personalized to the user, and is based on the maintained record of user interactions with the online session.
    Type: Grant
    Filed: May 18, 2015
    Date of Patent: March 20, 2018
    Assignee: ADOBE SYSTEMS INCORPORATED
    Inventors: Ajay Jain, Sumeet Gupta, Mili Sharma
  • Publication number: 20160344779
    Abstract: Users can participate in various different types of online sessions, such as webinars, massive open online courses (MOOCs), social learning sessions, and so forth. A record of interactions that the user has with an online session is maintained. During the online session, the user may become disengaged from the online session for various reasons, such as the user losing interest in the information being presented, the user becoming sidetracked due to other programs running on his or her computer or phone, and so forth. The techniques discussed herein detect that a user is not engaged in the online session and generate dynamic content to attempt to re-engage the user in the online session. This dynamic content is personalized to the user, and is based on the maintained record of user interactions with the online session.
    Type: Application
    Filed: May 18, 2015
    Publication date: November 24, 2016
    Inventors: Ajay Jain, Sumeet Gupta, Mili Sharma
  • Publication number: 20160261655
    Abstract: Disclosed are various embodiments for correlating the measured engagement of attendees to an online conference with the content of the online conference. In one implementation, a timeline is displayed in a user interface for at least a portion of the online conference. The timeline correlates the engagement of the attendees with the content of the online conference based on compiling values measured for engagement parameters of the respective attendees at defined time intervals during the online conference. Input is received identifying a point or interval of the timeline of the online conference. In response to receiving the input, content of the online conference associated with the point or interval is identified and displayed. Alternatively or in addition to displaying content, multiple, different ones of the engagement parameters for the point or interval are identified and have the respective values displayed.
    Type: Application
    Filed: March 3, 2015
    Publication date: September 8, 2016
    Inventors: Anurag Aggarwal, Ajay Jain, Sumeet Gupta, Mili Sharma
  • Patent number: 9298344
    Abstract: A computer implemented method and apparatus for enabling participation in a web conference as a virtual participant. The method comprises establishing a web conference comprising at least one virtual participant; receiving at least one message via a web conference user interface; displaying the message in the web conference user interface; and sending the message to the at least one virtual participant via a selected method of message delivery for the at least one virtual participant.
    Type: Grant
    Filed: June 10, 2013
    Date of Patent: March 29, 2016
    Assignee: ADOBE SYSTEMS INCORPORATED
    Inventors: Sumeet Gupta, Mili Sharma