Patents by Inventor Sumeet Kumar Gupta

Sumeet Kumar Gupta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11966714
    Abstract: A circuit of cells used as a memory array and capable of in-memory arithmetic which includes a plurality of signed ternary processing, each signed ternary processing cell includes a first memory cell, adapted to hold a first digital value, a second memory cell, adapted to hold a second digital value, wherein a binary combination of the first digital value and the second digital value establishes a first signed ternary operand, a signed ternary input forming a second signed ternary operand, and a signed ternary output, wherein the signed ternary output represents a signed multiplication of the first signed ternary operand and the second signed ternary operand, a sense circuit adapted to output a subtraction result.
    Type: Grant
    Filed: January 30, 2022
    Date of Patent: April 23, 2024
    Assignee: Purdue Research Foundation
    Inventors: Shubham Jain, Anand Raghunathan, Sumeet Kumar Gupta
  • Patent number: 11688445
    Abstract: A memory cell is disclosed which includes a semiconductor layer, a first electrode coupled to the semiconductor layer, a second electrode coupled to the semiconductor layer, wherein the first and second electrodes are separated from one another along a first axis and wherein the semiconductor layer extends beyond the first axis along a second axis substantially perpendicular to the first axis, thereby forming a first wing, a third electrode separated from the semiconductor layer by an insulating layer, a first magnetic tunnel junction (MTJ) disposed on the first wing, and a first read electrode coupled to the first MTJ.
    Type: Grant
    Filed: January 30, 2022
    Date of Patent: June 27, 2023
    Assignee: Purdue Research Foundation
    Inventors: Sandeep Krishna Thirumala, Sumeet Kumar Gupta, Yi-Tse Hung, Zhihong Chen
  • Publication number: 20220206751
    Abstract: A circuit of cells used as a memory array and capable of in-memory arithmetic is disclosed which includes a plurality of signed ternary processing, each signed ternary processing cell includes a first memory cell, adapted to hold a first digital value, a second memory cell, adapted to hold a second digital value, wherein a binary combination of the first digital value and the second digital value establishes a first signed ternary operand, a signed ternary input forming a second signed ternary operand, and a signed ternary output, wherein the signed ternary output represents a signed multiplication of the first signed ternary operand and the second signed ternary operand, a sense circuit adapted to output a subtraction result.
    Type: Application
    Filed: January 30, 2022
    Publication date: June 30, 2022
    Applicant: Purdue Research Foundation
    Inventors: Shubham Jain, Anand Raghunathan, Sumeet Kumar Gupta
  • Publication number: 20220157359
    Abstract: A memory cell is disclosed which includes a semiconductor layer, a first electrode coupled to the semiconductor layer, a second electrode coupled to the semiconductor layer, wherein the first and second electrodes are separated from one another along a first axis and wherein the semiconductor layer extends beyond the first axis along a second axis substantially perpendicular to the first axis, thereby forming a first wing, a third electrode separated from the semiconductor layer by an insulating layer, a first magnetic tunnel junction (MTJ) disposed on the first wing, and a first read electrode coupled to the first MTJ.
    Type: Application
    Filed: January 30, 2022
    Publication date: May 19, 2022
    Applicant: Purdue Research Foundation
    Inventors: Sandeep Krishna Thirumala, Sumeet Kumar Gupta, Yi-Tse Hung, Zhihong Chen
  • Patent number: 11296224
    Abstract: A polarization induced strain coupled two dimensional field effect transistor (PoSt FET) memory cell is disclosed which includes a transistor including a source contact, a drain contact, a gate contact, a back contact, a channel disposed atop the gate contact, wherein the channel and the gate are separated by an electrically insulating material, and a piezoelectric (PE)/ferroelectric(FE) (PE/FE) layer disposed between the gate contact and the back contact and configured to store bit information in form of ferroelectric polarization (P), wherein a ratio of cross-sectional area of the channel to cross-sectional area of the PE/FE layer is between about 0.03 to about 0.07.
    Type: Grant
    Filed: June 16, 2021
    Date of Patent: April 5, 2022
    Assignee: Purdue Research Foundation
    Inventors: Niharika Thakuria, Sumeet Kumar Gupta
  • Patent number: 11281429
    Abstract: A ternary processing cell used as a memory cell and capable of in-memory arithmetic is disclosed which includes a first memory cell, adapted to hold a first digital value, a second memory cell, adapted to hold a second digital value, wherein a binary combination of the first digital value and the second digital value establishes a first ternary operand, a ternary input establishing a second ternary operand, and a ternary output, wherein the ternary output represents a multiplication of the first ternary operand and the second ternary operand.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: March 22, 2022
    Assignee: Purdue Research Foundation
    Inventors: Shubham Jain, Anand Raghunathan, Sumeet Kumar Gupta
  • Patent number: 11250896
    Abstract: A memory cell is disclosed which includes a conductive layer, an insulating layer disposed atop the conducting layer, a semiconductor layer disposed atop the insulating layer, a first electrode coupled to the semiconductor layer, a second electrode coupled to the semiconductor layer, wherein the first and second electrodes are separated from one another and wherein the semiconductor layer extends beyond the first and second electrodes forming a first wing, a third electrode coupled to the conductive layer, a first magnetic tunnel junction (MTJ) disposed on the first wing, and a first read electrode coupled to the first MTJ.
    Type: Grant
    Filed: June 23, 2020
    Date of Patent: February 15, 2022
    Assignee: Purdue Research Foundation
    Inventors: Sandeep Krishna Thirumala, Sumeet Kumar Gupta, Yi-Tse Hung, Zhihong Chen
  • Publication number: 20210089272
    Abstract: A ternary processing cell used as a memory cell and capable of in-memory arithmetic is disclosed which includes a first memory cell, adapted to hold a first digital value, a second memory cell, adapted to hold a second digital value, wherein a binary combination of the first digital value and the second digital value establishes a first ternary operand, a ternary input establishing a second ternary operand, and a ternary output, wherein the ternary output represents a multiplication of the first ternary operand and the second ternary operand.
    Type: Application
    Filed: September 25, 2019
    Publication date: March 25, 2021
    Applicant: Purdue Research Foundation
    Inventors: Shubham Jain, Anand Raghunathan, Sumeet Kumar Gupta
  • Publication number: 20200402560
    Abstract: A memory cell is disclosed which includes a conductive layer, an insulating layer disposed atop the conducting layer, a semiconductor layer disposed atop the insulating layer, a first electrode coupled to the semiconductor layer, a second electrode coupled to the semiconductor layer, wherein the first and second electrodes are separated from one another and wherein the semiconductor layer extends beyond the first and second electrodes forming a first wing, a third electrode coupled to the conductive layer, a first magnetic tunnel junction (MTJ) disposed on the first wing, and a first read electrode coupled to the first MTJ.
    Type: Application
    Filed: June 23, 2020
    Publication date: December 24, 2020
    Applicant: Purdue Research Foundation
    Inventors: Sandeep Krishna Thirumala, Sumeet Kumar Gupta, Yi-Tse Hung, Zhihong Chen
  • Patent number: 10839880
    Abstract: A sense amplifier utilizes a phase transition material (PTM) in conjunction with CMOS circuits to provide a precise sensing threshold. The sense amplifier can be used in memory applications to sense states of stored bits with high accuracy and robustness. In one sense amplifier, a first diode-connected transistor has gate and drain nodes coupled to an input node of the sense amplifier, a second transistor has a gate node coupled to the gate node of the first diode-connected transistor, and the PTM is coupled to the source node of the second transistor. In another sense amplifier, a first transistor has a gate node coupled to an input node of the sense amplifier, a PTM is coupled to the source node of the first transistor, and an output stage including an inverter is coupled between a drain node of the first transistor and an output node of the sense amplifier.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: November 17, 2020
    Assignee: The Penn State Research Foundation
    Inventors: Sumeet Kumar Gupta, Ahmedullah Aziz, Nikhil Shukla, Suman Datta, Xueqing Li, Vijaykrishnan Narayanan
  • Publication number: 20190172514
    Abstract: A sense amplifier utilizes a phase transition material (PTM) in conjunction with CMOS circuits to provide a precise sensing threshold. The sense amplifier can be used in memory applications to sense states of stored bits with high accuracy and robustness. In one sense amplifier, a first diode-connected transistor has gate and drain nodes coupled to an input node of the sense amplifier, a second transistor has a gate node coupled to the gate node of the first diode-connected transistor, and the PTM is coupled to the source node of the second transistor. In another sense amplifier, a first transistor has a gate node coupled to an input node of the sense amplifier, a PTM is coupled to the source node of the first transistor, and an output stage including an inverter is coupled between a drain node of the first transistor and an output node of the sense amplifier.
    Type: Application
    Filed: January 31, 2019
    Publication date: June 6, 2019
    Inventors: Sumeet Kumar GUPTA, Ahmedullah AZIZ, Nikhil SHUKLA, Suman DATTA, Xueqing LI, Vijaykrishnan NARAYANAN
  • Patent number: 10262714
    Abstract: A sense amplifier utilizes a phase transition material (PTM) in conjunction with CMOS circuits to provide a precise sensing threshold. The sense amplifier can be used in memory applications to sense states of stored bits with high accuracy and robustness. In one sense amplifier, a first diode-connected transistor has gate and drain nodes coupled to an input node of the sense amplifier, a second transistor has a gate node coupled to the gate node of the first diode-connected transistor, and the PTM is coupled to the source node of the second transistor. In another sense amplifier, a first transistor has a gate node coupled to an input node of the sense amplifier, a PTM is coupled to the source node of the first transistor, and an output stage including an inverter is coupled between a drain node of the first transistor and an output node of the sense amplifier.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: April 16, 2019
    Assignee: The Penn State Research Foundation
    Inventors: Sumeet Kumar Gupta, Ahmedullah Aziz, Nikhil Shukla, Suman Datta, Xueqing Li, Vijaykrishnan Narayanan
  • Publication number: 20170352394
    Abstract: A sense amplifier utilizes a phase transition material (PTM) in conjunction with CMOS circuits to provide a precise sensing threshold. The sense amplifier can be used in memory applications to sense states of stored bits with high accuracy and robustness. In one sense amplifier, a first diode-connected transistor has gate and drain nodes coupled to an input node of the sense amplifier, a second transistor has a gate node coupled to the gate node of the first diode-connected transistor, and the PTM is coupled to the source node of the second transistor. In another sense amplifier, a first transistor has a gate node coupled to an input node of the sense amplifier, a PTM is coupled to the source node of the first transistor, and an output stage including an inverter is coupled between a drain node of the first transistor and an output node of the sense amplifier.
    Type: Application
    Filed: June 5, 2017
    Publication date: December 7, 2017
    Inventors: Sumeet Kumar GUPTA, Ahmedullah AZIZ, Nikhil SHUKLA, Suman DATTA, Xueqing LI, Vijaykrishnan NARAYANAN
  • Patent number: D710795
    Type: Grant
    Filed: August 23, 2013
    Date of Patent: August 12, 2014
    Inventors: Sumeet Kumar Gupta, Joseph Bryant Carrillo
  • Patent number: D742312
    Type: Grant
    Filed: January 5, 2015
    Date of Patent: November 3, 2015
    Inventors: Sumeet Kumar Gupta, Joseph Bryant Carrillo
  • Patent number: D756909
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: May 24, 2016
    Inventors: Sumeet Kumar Gupta, Joseph Bryant Carrillo
  • Patent number: D756910
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: May 24, 2016
    Inventors: Sumeet Kumar Gupta, Joseph Bryant Carrillo
  • Patent number: D756911
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: May 24, 2016
    Inventors: Sumeet Kumar Gupta, Joseph Bryant Carrillo
  • Patent number: D783525
    Type: Grant
    Filed: October 29, 2015
    Date of Patent: April 11, 2017
    Inventors: Sumeet Kumar Gupta, Joseph Bryant Carrillo
  • Patent number: D823239
    Type: Grant
    Filed: September 6, 2016
    Date of Patent: July 17, 2018
    Inventors: Sumeet Kumar Gupta, Joseph Bryant Carrillo