Patents by Inventor Sumesh Subramanian

Sumesh Subramanian has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11409560
    Abstract: In one embodiment, a processor includes a current protection controller to: receive instruction width information and instruction type information associated with one or more instructions stored in an instruction queue prior to execution of the one or more instructions by an execution circuit; determine a power license level for the core based on the corresponding instruction width information and the instruction type information; generate a request for a license for the core corresponding to the power license level; and communicate the request to a power controller when the one or more instructions are non-speculative, and defer communication of the request when at least one of the one or more instructions is speculative. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: August 9, 2022
    Assignee: Intel Corporation
    Inventors: Krishnamurthy Jambur Sathyanarayana, Robert Valentine, Alexander Gendler, Shmuel Zobel, Gavri Berger, Ian M. Steiner, Nikhil Gupta, Eyal Hadas, Edo Hachamo, Sumesh Subramanian
  • Publication number: 20220114033
    Abstract: An apparatus, one or more computer readable media, a distributed edge computing system, and a method. The apparatus includes one or more processors to determine dependencies between sets of tasks of a plurality of tasks to be executed by a plurality of cores of a network; determine latency deadlines of respective ones of the plurality of tasks; and determine an allocation of individual ones of the plurality of among the plurality of cores for execution based on the dependencies and based on the latency deadlines.
    Type: Application
    Filed: December 22, 2021
    Publication date: April 14, 2022
    Inventors: Marius O. Arvinte, Maruti Gupta Hyde, Mustafa Riza Akdeniz, Arjun Anand, Ravikumar Balakrishnan, Nageen Himayat, Sumesh Subramanian, Alexander Bachmutsky, John M. Belstner
  • Publication number: 20200310872
    Abstract: In one embodiment, a processor includes a current protection controller to: receive instruction width information and instruction type information associated with one or more instructions stored in an instruction queue prior to execution of the one or more instructions by an execution circuit; determine a power license level for the core based on the corresponding instruction width information and the instruction type information; generate a request for a license for the core corresponding to the power license level; and communicate the request to a power controller when the one or more instructions are non-speculative, and defer communication of the request when at least one of the one or more instructions is speculative. Other embodiments are described and claimed.
    Type: Application
    Filed: March 28, 2019
    Publication date: October 1, 2020
    Inventors: Krishnamurthy Jambur Sathyanarayana, Robert Valentine, Alexander Gendler, Shmuel Zobel, Gavri Berger, Ian M. Steiner, Nikhil Gupta, Eyal Hadas, Edo Hachamo, Sumesh Subramanian
  • Patent number: 8869163
    Abstract: There is provided a system and method for providing an integrated environment for execution monitoring and profiling of applications running on multi-processor system-on-chips. There is provided a method comprising obtaining task execution data of an application, the task execution data including a plurality of task executions assigned to a plurality of hardware resources, showing a scheduler view of the plurality of task executions on a display, receiving a modification request for a selected task execution from the plurality of task executions, reassigning the plurality of task executions to the plurality of hardware resources based on implementing the modification request, and updating the scheduler view on the display. As a result, the high level results of specific low level optimizations may be tested and retried to discover which optimization routes provide the greatest benefits.
    Type: Grant
    Filed: July 19, 2011
    Date of Patent: October 21, 2014
    Assignee: Mindspeed Technologies, Inc.
    Inventors: Abdulnour Toukmaji, Dmytro Lysenko, Sumesh Subramanian
  • Publication number: 20120185864
    Abstract: There is provided a system and method for providing an integrated environment for execution monitoring and profiling of applications running on multi-processor system-on-chips. There is provided a method comprising obtaining task execution data of an application, the task execution data including a plurality of task executions assigned to a plurality of hardware resources, showing a scheduler view of the plurality of task executions on a display, receiving a modification request for a selected task execution from the plurality of task executions, reassigning the plurality of task executions to the plurality of hardware resources based on implementing the modification request, and updating the scheduler view on the display. As a result, the high level results of specific low level optimizations may be tested and retried to discover which optimization routes provide the greatest benefits.
    Type: Application
    Filed: July 19, 2011
    Publication date: July 19, 2012
    Applicant: MINDSPEED TECHNOLOGIES, INC.
    Inventors: Abdulnour Toukmaji, Dmytro Lysenko, Sumesh Subramanian