Abstract: The detector is reduced in DC power consumption when an input signal is at a low amplitude level. The detector includes first and second input terminals, first and second transistors, and a load element. The first and second input terminals are supplied with complementary input signals reverse to each other in phase. The first input terminal is connected to the first input electrode of the first transistor and the second input electrode of the second transistor. The second input terminal is connected to the second input electrode of the first transistor and the first input electrode of the second transistor. The load element is connected between output electrodes of the transistors and an operating voltage point. A detection voltage resulting from full-wave rectification arises from a circuit node. In the condition where a signal input to the input terminals is at a low amplitude level, the transistors are both in OFF state. Thus, DC power consumption is reduced.

Abstract: The detector is reduced in DC power consumption when an input signal is at a low amplitude level. The detector includes first and second input terminals, first and second transistors, and a load element. The first and second input terminals are supplied with complementary input signals reverse to each other in phase. The first input terminal is connected to the first input electrode of the first transistor and the second input electrode of the second transistor. The second input terminal is connected to the second input electrode of the first transistor and the first input electrode of the second transistor. The load element is connected between output electrodes of the transistors and an operating voltage point. A detection voltage resulting from full-wave rectification arises from a circuit node. In the condition where a signal input to the input terminals is at a low amplitude level, the transistors are both in OFF state. Thus, DC power consumption is reduced.