Patents by Inventor Sumie Hirai

Sumie Hirai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6711815
    Abstract: A printed wired board is provided, in which an area for extracting liens for plating of the printed wired board is made small and at the same time the number of the extracting lines for plating within a packaging area is made small, resulting in an improvement of wiring efficiency. The circuit pattern formed on an insulating film has window portion and is not formed toward the periphery of the insulating film, and a bonding pad is electroplated, where the bonding pads are to be connected with a center-pad of a semiconductor by a bonding wire through the window portion. Accordingly, even when the shrinkage of semiconductor packages or narrow ball pitch is forwarded, the degree of freedom of drawing of circuit pattern in the printed wired board can be made large.
    Type: Grant
    Filed: August 22, 2002
    Date of Patent: March 30, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Sumie Hirai, Jun Ohmori
  • Publication number: 20030056976
    Abstract: A fabricating method of semiconductor devices in which pads of a semiconductor chip of center-pad structure and bonding pads of a printed wired board are connected electrically. In an area of the printed wired board corresponding to the pads of the chip an extracting line for plating is formed, and circuit pattern electrically connecting the extracting line, terminal portions for external input/output and bonding pads is formed. The steps of electroplating the terminal portions and the bonding pads while supplying electricity from the extracting line, and removing the area of the printed wired board corresponding to the pads of the chip together with the extracting line to form a window portion are further comprised. A fabricating method of semiconductor devices in which to pads of a semiconductor chip of center-pad structure leads extending from circuit pattern of a printed wired board is connected.
    Type: Application
    Filed: August 22, 2002
    Publication date: March 27, 2003
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Sumie Hirai, Jun Ohmori
  • Publication number: 20020189852
    Abstract: A fabricating method of semiconductor devices in which pads of a semiconductor chip of center-pad structure and bonding pads of a printed wired board are connected electrically. In an area of the printed wired board corresponding to the pads of the chip an extracting line for plating is formed, and circuit pattern electrically connecting the extracting line, terminal portions for external input/output and bonding pads is formed. The steps of electroplating the terminal portions and the bonding pads while supplying electricity from the extracting line, and removing the area of the printed wired board corresponding to the pads of the chip together with the extracting line to form a window portion are further comprised. A fabricating method of semiconductor devices in which to pads of a semiconductor chip of center-pad structure leads extending from circuit pattern of a printed wired board is connected.
    Type: Application
    Filed: August 22, 2002
    Publication date: December 19, 2002
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Sumie Hirai, Jun Ohmori
  • Patent number: 6462283
    Abstract: A printed wired board is provided, in which an area for extracting lines for plating of the printed wired board is made small and at the same time the number of the extracting lines for plating within a packaging area is made small, resulting in an improvement of wiring efficiency. The circuit pattern formed on an insulating film has a window portion and is not formed toward the periphery of the insulating film, and a bonding pad is electroplated, where the bonding pads are to be connected with a center-pad of a semiconductor by a bonding wire through the window portion. Accordingly, even when the shrinkage of semiconductor packages or narrow ball pitch is forwarded, the degree of freedom of drawing of circuit pattern in the printed wired board can be made large.
    Type: Grant
    Filed: September 3, 1999
    Date of Patent: October 8, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Sumie Hirai, Jun Ohmori