Patents by Inventor Sumikazu Hosoyamada
Sumikazu Hosoyamada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10236231Abstract: A semiconductor device includes a lead frame; a circuit board located on the lead frame; a power device that includes a switching element and is mounted on the circuit board via a bump located between the power device and the circuit board; and a heat releasing member connected to the power device. The circuit board may be a multi-layer wiring board. The circuit board may include a capacitor element, a resistor element, an inductor element, a diode element and a switching element.Type: GrantFiled: June 30, 2017Date of Patent: March 19, 2019Assignee: J-DEVICES CORPORATIONInventors: Takeshi Miyakoshi, Sumikazu Hosoyamada, Yoshikazu Kumagaya, Tomoshige Chikai, Shingo Nakamura, Hiroaki Matsubara, Shotaro Sakumoto
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Patent number: 10134710Abstract: A stacked semiconductor package in an embodiment includes a first semiconductor package including a first circuit board and a first semiconductor element mounted on the first circuit board; and a second semiconductor package including a second circuit board and a second semiconductor element mounted on the second circuit board, the second semiconductor package being stacked on the first semiconductor package. The first semiconductor package further includes a sealing resin sealing the first semiconductor element; a conductive layer located in contact with the sealing resin; and a thermal via connected to the conductive layer and located on the first circuit board.Type: GrantFiled: February 2, 2017Date of Patent: November 20, 2018Assignee: J-DEVICES CORPORATIONInventors: Takeshi Miyakoshi, Sumikazu Hosoyamada, Yoshikazu Kumagaya, Tomoshige Chikai, Shingo Nakamura, Hiroaki Matsubara, Shotaro Sakumoto
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Publication number: 20170301599Abstract: A semiconductor device includes a lead frame; a circuit board located on the lead frame; a power device that includes a switching element and is mounted on the circuit board via a bump located between the power device and the circuit board; and a heat releasing member connected to the power device. The circuit board may be a multi-layer wiring board. The circuit board may include a capacitor element, a resistor element, an inductor element, a diode element and a switching element.Type: ApplicationFiled: June 30, 2017Publication date: October 19, 2017Applicant: J-DEVICES CORPORATIONInventors: Takeshi MIYAKOSHI, Sumikazu HOSOYAMADA, Yoshikazu KUMAGAYA, Tomoshige CHIKAI, Shingo NAKAMURA, Hiroaki MATSUBARA, Shotaro SAKUMOTO
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Publication number: 20170148766Abstract: A stacked semiconductor package in an embodiment includes a first semiconductor package including a first circuit board and a first semiconductor element mounted on the first circuit board; and a second semiconductor package including a second circuit board and a second semiconductor element mounted on the second circuit board, the second semiconductor package being stacked on the first semiconductor package. The first semiconductor package further includes a sealing resin sealing the first semiconductor element; a conductive layer located in contact with the sealing resin; and a thermal via connected to the conductive layer and located on the first circuit board.Type: ApplicationFiled: February 2, 2017Publication date: May 25, 2017Applicant: J-DEVICES CORPORATIONInventors: Takeshi MIYAKOSHI, Sumikazu HOSOYAMADA, Yoshikazu KUMAGAYA, Tomoshige CHIKAI, Shingo NAKAMURA, Hiroaki MATSUBARA, Shotaro SAKUMOTO
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Patent number: 9635762Abstract: A stacked semiconductor package includes a first semiconductor package including a first circuit board and a first semiconductor device mounted on the first circuit board; a second semiconductor package including a second circuit board and a second semiconductor device mounted on the second circuit board, the second semiconductor package being stacked on the first semiconductor package; and a heat transfer member provided on the first semiconductor device and a part of the first circuit board, the part being around the first semiconductor device.Type: GrantFiled: July 20, 2015Date of Patent: April 25, 2017Assignee: J-DEVICES CORPORATIONInventors: Shinji Watanabe, Sumikazu Hosoyamada, Shingo Nakamura, Hiroshi Demachi, Takeshi Miyakoshi, Tomoshige Chikai, Kiminori Ishido, Hiroaki Matsubara, Takashi Nakamura, Hirokazu Honda, Yoshikazu Kumagaya, Shotaro Sakumoto, Toshihiro Iwasaki, Michiaki Tamakawa
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Patent number: 9601450Abstract: A stacked semiconductor package in an embodiment includes a first semiconductor package including a first circuit board and a first semiconductor element mounted on the first circuit board; and a second semiconductor package including a second circuit board and a second semiconductor element mounted on the second circuit board, the second semiconductor package being stacked on the first semiconductor package. The first semiconductor package further includes a sealing resin sealing the first semiconductor element; a conductive layer located in contact with the sealing resin; and a thermal via connected to the conductive layer and located on the first circuit board.Type: GrantFiled: March 26, 2015Date of Patent: March 21, 2017Assignee: J-DEVICES CORPORATIONInventors: Takeshi Miyakoshi, Sumikazu Hosoyamada, Yoshikazu Kumagaya, Tomoshige Chikai, Shingo Nakamura, Hiroaki Matsubara, Shotaro Sakumoto
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Patent number: 9368474Abstract: A manufacturing method for a semiconductor device of the present invention includes: preparing a semiconductor wafer including an electrode formed therein; electrically connecting a first semiconductor element formed in a semiconductor chip and the electrode formed in the semiconductor wafer; filling a gap between the semiconductor wafer and the semiconductor chip with a first insulating resin layer; forming a second insulating resin layer on the semiconductor wafer; grinding the second insulating resin layer and the semiconductor chip until a thickness of the semiconductor chip reaches a predetermined thickness; forming a first insulating layer on the second insulating resin layer and the semiconductor chip; forming a line on the first insulating layer connected with a conductive material filled an opening in the first insulating layer and the second insulating resin layer to expose the electrode; and grinding the semiconductor wafer until a thickness of the semiconductor wafer reaches a predetermined thicknType: GrantFiled: September 10, 2015Date of Patent: June 14, 2016Assignee: J-DEVICES CORPORATIONInventors: Hiroaki Matsubara, Tomoshige Chikai, Kiminori Ishido, Takashi Nakamura, Hirokazu Honda, Hiroshi Demachi, Yoshikazu Kumagaya, Shotaro Sakumoto, Shinji Watanabe, Sumikazu Hosoyamada, Shingo Nakamura, Takeshi Miyakoshi, Toshihiro Iwasaki, Michiaki Tamakawa
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Patent number: 9362200Abstract: A semiconductor package includes a support substrate arranged with a first aperture reaching a semiconductor device on a rear side, the semiconductor device is bonded via an adhesive to a surface of the support substrate, an insulating layer covering the semiconductor device, and wiring for connecting the semiconductor device and an external terminal through the insulating layer. The adhesive may form a part of the first aperture. In addition, a heat dissipation part may be arranged in the first aperture and a metal material may be filled in the first aperture.Type: GrantFiled: June 19, 2015Date of Patent: June 7, 2016Assignee: J-DEVICES CORPORATIONInventors: Hirokazu Honda, Shinji Watanabe, Toshihiro Iwasaki, Kiminori Ishido, Koichiro Niwa, Takeshi Miyakoshi, Sumikazu Hosoyamada, Yoshikazu Kumagaya, Tomoshige Chikai, Shingo Nakamura, Shotaro Sakumoto, Hiroaki Matsubara
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Publication number: 20160079204Abstract: A manufacturing method for a semiconductor device of the present invention includes: preparing a semiconductor wafer including an electrode formed therein; electrically connecting a first semiconductor element formed in a semiconductor chip and the electrode formed in the semiconductor wafer; filling a gap between the semiconductor wafer and the semiconductor chip with a first insulating resin layer; forming a second insulating resin layer on the semiconductor wafer; grinding the second insulating resin layer and the semiconductor chip until a thickness of the semiconductor chip reaches a predetermined thickness; forming a first insulating layer on the second insulating resin layer and the semiconductor chip; forming a line on the first insulating layer connected with a conductive material filled an opening in the first insulating layer and the second insulating resin layer to expose the electrode; and grinding the semiconductor wafer until a thickness of the semiconductor wafer reaches a predetermined thicknType: ApplicationFiled: September 10, 2015Publication date: March 17, 2016Inventors: Hiroaki Matsubara, Tomoshige Chikai, Kiminori Ishido, Takashi Nakamura, Hirokazu Honda, Hiroshi Demachi, Yoshikazu Kumagaya, Shotaro Sakumoto, Shinji Watanabe, Sumikazu Hosoyamada, Shingo Nakamura, Takeshi Miyakoshi, Toshihiro Iwasaki, Michiaki Tamakawa
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Publication number: 20160027715Abstract: A stacked semiconductor package includes a first semiconductor package including a first circuit board and a first semiconductor device mounted on the first circuit board; a second semiconductor package including a second circuit board and a second semiconductor device mounted on the second circuit board, the second semiconductor package being stacked on the first semiconductor package; and a heat transfer member provided on the first semiconductor device and a part of the first circuit board, the part being around the first semiconductor device.Type: ApplicationFiled: July 20, 2015Publication date: January 28, 2016Inventors: Shinji WATANABE, Sumikazu HOSOYAMADA, Shingo NAKAMURA, Hiroshi DEMACHI, Takeshi MIYAKOSHI, Tomoshige CHIKAI, Kiminori ISHIDO, Hiroaki MATSUBARA, Takashi NAKAMURA, Hirokazu HONDA, Yoshikazu KUMAGAYA, Shotaro SAKUMOTO, Toshihiro IWASAKI, Michiaki TAMAKAWA
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Publication number: 20150371934Abstract: A semiconductor package includes a support substrate arranged with a first aperture reaching a semiconductor device on a rear side, the semiconductor device is bonded via an adhesive to a surface of the support substrate, an insulating layer covering the semiconductor device, and wiring for connecting the semiconductor device and an external terminal through the insulating layer. The adhesive may form a part of the first aperture. In addition, a heat dissipation part may be arranged in the first aperture and a metal material may be filled in the first aperture.Type: ApplicationFiled: June 19, 2015Publication date: December 24, 2015Inventors: Hirokazu HONDA, Shinji WATANABE, Toshihiro IWASAKI, Kiminori ISHIDO, Koichiro NIWA, Takeshi MIYAKOSHI, Sumikazu HOSOYAMADA, Yoshikazu KUMAGAYA, Tomoshige CHIKAI, Shingo NAKAMURA, Shotaro SAKUMOTO, Hiroaki MATSUBARA
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Publication number: 20150279759Abstract: A stacked semiconductor package in an embodiment includes a first semiconductor package including a first circuit board and a first semiconductor element mounted on the first circuit board; and a second semiconductor package including a second circuit board and a second semiconductor element mounted on the second circuit board, the second semiconductor package being stacked on the first semiconductor package. The first semiconductor package further includes a sealing resin sealing the first semiconductor element; a conductive layer located in contact with the sealing resin; and a thermal via connected to the conductive layer and located on the first circuit board.Type: ApplicationFiled: March 26, 2015Publication date: October 1, 2015Applicant: J-DEVICES CORPORATIONInventors: Takeshi Miyakoshi, Sumikazu HOSOYAMADA, Yoshikazu KUMAGAYA, Tomoshige CHIKAI, Shingo NAKAMURA, Hiroaki MATSUBARA, Shotaro SAKUMOTO
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Publication number: 20150243576Abstract: A semiconductor device includes a lead frame; a circuit board located on the lead frame; a power device that includes a switching element and is mounted on the circuit board via a bump located between the power device and the circuit board; and a heat releasing member connected to the power device. The circuit board may be a multi-layer wiring board. The circuit board may include a capacitor element, a resistor element, an inductor element, a diode element and a switching element.Type: ApplicationFiled: February 12, 2015Publication date: August 27, 2015Applicant: J-DEVICES CORPORATIONInventors: Takeshi MIYAKOSHI, Sumikazu HOSOYAMADA, Yoshikazu KUMAGAYA, Tomoshige CHIKAI, Shingo NAKAMURA, Hiroaki MATSUBARA
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Patent number: 7476811Abstract: A semiconductor device includes: a semiconductor element; a circuit substrate having a cavity at a center thereof; a heat radiating member having the semiconductor element bonded at a central portion thereof; and a sealing resin configured to seal the semiconductor element in the cavity. A configuration is provided such that a bonding resin may be disposed in a gap portion which communicates with the cavity between the circuit substrate and the heat radiating member, and by means of a bonding force of the bonding resin, the heat radiating member is permanently fixed to the circuit substrate.Type: GrantFiled: March 14, 2005Date of Patent: January 13, 2009Assignee: Fujitsu LimitedInventors: Yoshihiro Kubota, Kazuto Tsuji, Sumikazu Hosoyamada
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Patent number: 7361980Abstract: A semiconductor device comprises a semiconductor chip in which a circuit part provided in a center of the semiconductor chip is connected with power-supply lines and power-supply electrodes to supply power from an external power source to the circuit part. A substrate is provided for carrying the semiconductor chip thereon and provided so that first terminals in a region encircling the semiconductor chip are electrically connected to the power-supply electrodes. A first opening is formed on the power-supply line in a center of the circuit part. A second opening is formed on the power-supply line at a peripheral part of the circuit part. A conductor layer is electrically connected to second terminals in the region encircling the semiconductor chip on the substrate, and provided so that the power-supply line in the first opening and the power-supply line in the second opening are connected together.Type: GrantFiled: May 26, 2005Date of Patent: April 22, 2008Assignee: Fujitsu LimitedInventors: Sumikazu Hosoyamada, Kazuto Tsuji, Yoshihiro Kubota
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Publication number: 20070114642Abstract: A semiconductor element has a circuit formation surface on which electrode terminals are arranged in a peripheral part thereof. The semiconductor element is encapsulated by a mold resin on a substrate which has openings at positions corresponding to the electrodes of the semiconductor element. The semiconductor element is mounted to the substrate in a state where the circuit formation surface faces the substrate and the electrode terminals are positioned at the openings and a back surface opposite to the circuit formation surface of the semiconductor element is exposed from the mold resin. A heat-emitting member formed of a metal plate is provided on a surface of the substrate opposite to a surface on which the semiconductor element is mounted. The surface of the heat-emitting member being exposed from the mold resin.Type: ApplicationFiled: January 19, 2007Publication date: May 24, 2007Applicant: FUJITSU LIMITEDInventors: Sumikazu Hosoyamada, Yoshitsugu Kato, Mitsuo Abe, Kazuto Tsuji, Masaharu Minamizawa, Toshio Hamano, Toshiyuki Honda, Katsuro Hiraiwa, Masashi Takenaka
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Patent number: 7193320Abstract: A semiconductor element has a circuit formation surface on which electrode terminals are arranged in a peripheral part thereof. The semiconductor element is encapsulated by a mold resin on a substrate which has openings at positions corresponding to the electrodes of the semiconductor element. The semiconductor element is mounted to the substrate in a state where the circuit formation surface faces the substrate and the electrode terminals are positioned at the openings and a back surface opposite to the circuit formation surface of the semiconductor element is exposed from the mold resin. A heat-emitting member formed of a metal plate is provided on a surface of the substrate opposite to a surface on which the semiconductor element is mounted. The surface of the heat-emitting member being exposed from the mold resin.Type: GrantFiled: January 28, 2003Date of Patent: March 20, 2007Assignee: Fujitsu LimitedInventors: Sumikazu Hosoyamada, Yoshitsugu Kato, Mitsuo Abe, Kazuto Tsuji, Masaharu Minamizawa, Toshio Hamano, Toshiyuki Honda, Katsuro Hiraiwa, Masashi Takenaka
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Publication number: 20060137902Abstract: A semiconductor device includes: a semiconductor element; a circuit substrate having a cavity at a center thereof; a heat radiating member having the semiconductor element bonded at a central portion thereof; and a sealing resin configured to seal the semiconductor element in the cavity. A configuration is provided such that a bonding resin may be disposed in a gap portion which communicates with the cavity between the circuit substrate and the heat radiating member, and by means of a bonding force of the bonding resin, the heat radiating member is permanently fixed to the circuit substrate.Type: ApplicationFiled: March 14, 2005Publication date: June 29, 2006Applicant: FUJITSU LIMITEDInventors: Yoshihiro Kubota, Kazuto Tsuji, Sumikazu Hosoyamada
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Patent number: 7042102Abstract: In a semiconductor device, bonding-wires can be applied parallel to each other to electrodes of high-speed signal lines when mounting a highly densified semiconductor element on a low-cost substrate while reducing a length of the bonding-wires. An impedance-matched substrate having wiring that impedance-matched with circuits of a semiconductor element is mounted on a substrate. A plurality of first metal wires connect between first electrodes of the semiconductor element and electrodes of the substrate. A plurality of second metal wires connect between second electrodes of the semiconductor element and first electrodes of the impedance-matched substrate. A plurality of third metal wires connect between second electrodes of the impedance-matched substrate and electrodes of the substrate. The second metal wires extend parallel to each other, and the third metal wires also extend parallel to each other.Type: GrantFiled: October 25, 2004Date of Patent: May 9, 2006Assignee: Fujitsu LimitedInventors: Kazuto Tsuji, Yoshihiro Kubota, Kenji Asada, Sumikazu Hosoyamada
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Publication number: 20050280034Abstract: A semiconductor device comprises a semiconductor chip in which a circuit part provided in a center of the semiconductor chip is connected with power-supply lines and power-supply electrodes to supply power from an external power source to the circuit part. A substrate is provided for carrying the semiconductor chip thereon and provided so that first terminals in a region encircling the semiconductor chip are electrically connected to the power-supply electrodes. A first opening is formed on the power-supply line in a center of the circuit part. A second opening is formed on the power-supply line at a peripheral part of the circuit part. A conductor layer is electrically connected to second terminals in the region encircling the semiconductor chip on the substrate, and provided so that the power-supply line in the first opening and the power-supply line in the second opening are connected together.Type: ApplicationFiled: May 26, 2005Publication date: December 22, 2005Applicant: FUJITSU LIMITEDInventors: Sumikazu Hosoyamada, Kazuto Tsuji, Yoshihiro Kubota