Abstract: A semiconductor memory device according to an embodiment includes: a driver for supplying a voltage, the driver in the first step, when a current flows through the first substring, the second substring, the third substring, or the fourth substring, performing a second step of applying the first voltage to the bit line, applying a fourth voltage higher than the third voltage to the third select gate line, the fourth select gate line, the fifth select gate line, and the sixth select gate line, and applying a fifth voltage higher than the third voltage and lower than the fourth voltage to the first word lines and the second word lines.

Abstract: A semiconductor memory device includes a semiconductor pillar including first and second memory cells electrically connected in series and formed on opposite sides of the semiconductor pillar, first word lines connected to the first memory cells, respectively, and second word lines connected to the second memory cells, respectively. A verify operation includes a channel clean operation for supplying a reference voltage to a semiconductor channel shared by the first and second memory cells followed by at least first and second sense operation for determining whether a threshold voltage of a target memory cell has reached first and second threshold voltage states, respectively, then a second channel clean operation for supplying the reference voltage to the semiconductor channel, and then at least a third sense operation for determining whether the threshold voltage of the target memory cell has reached a third threshold voltage state.

Abstract: A semiconductor memory device according to an embodiment includes: a driver for supplying a voltage, the driver in the first step, when a current flows through the first substring, the second substring, the third substring, or the fourth substring, performing a second step of applying the first voltage to the bit line, applying a fourth voltage higher than the third voltage to the third select gate line, the fourth select gate line, the fifth select gate line, and the sixth select gate line, and applying a fifth voltage higher than the third voltage and lower than the fourth voltage to the first word lines and the second word lines.

Abstract: A semiconductor memory device includes a semiconductor pillar including first and second memory cells electrically connected in series and formed on opposite sides of the semiconductor pillar, first word lines connected to the first memory cells, respectively, and second word lines connected to the second memory cells, respectively. A verify operation includes a channel clean operation for supplying a reference voltage to a semiconductor channel shared by the first and second memory cells followed by at least first and second sense operation for determining whether a threshold voltage of a target memory cell has reached first and second threshold voltage states, respectively, then a second channel clean operation for supplying the reference voltage to the semiconductor channel, and then at least a third sense operation for determining whether the threshold voltage of the target memory cell has reached a third threshold voltage state.

Abstract: During a writing operation to change a resistance of a part of a variable resistance material film facing a first word line, the semiconductor storage device applies a first voltage to the first word line, applies a second voltage to a second word line, and applies a third voltage to a third word line. The first, second, and third word lines are stacked above a substrate. The second word line is adjacent to the first word line in the stacking direction. The third word line is not adjacent to the first word line in the stacking direction.

Abstract: A semiconductor storage device includes a stacked body and a columnar body. The stacked body includes a plurality of conductive layers spaced apart from each other in a stacking direction. The columnar body penetrates the stacked body in the stacking direction. The columnar body includes a columnar ferroelectric film, a semiconductor film disposed between the ferroelectric film and the conductive layers, and an insulating film disposed between the semiconductor film and the conductive layers.

Abstract: During a writing operation to change a resistance of a part of a variable resistance material film facing a first word line, the semiconductor storage device applies a first voltage to the first word line, applies a second voltage to a second word line, and applies a third voltage to a third word line. The first, second, and third word lines are stacked above a substrate. The second word line is adjacent to the first word line in the stacking direction. The third word line is not adjacent to the first word line in the stacking direction.

Abstract: A semiconductor storage device includes a stacked body and a columnar body. The stacked body includes a plurality of conductive layers spaced apart from each other in a stacking direction. The columnar body penetrates the stacked body in the stacking direction. The columnar body includes a columnar ferroelectric film, a semiconductor film disposed between the ferroelectric film and the conductive layers, and an insulating film disposed between the semiconductor film and the conductive layers.

Abstract: A magnetic memory device includes a magnetic thin wire including magnetic domains along a direction in which the magnetic thin wire extends. Magnetization directions of the magnetic domains are variable. A magnetic tunnel junction (MTJ) structure includes a pinned layer with a fixed magnetization direction and an insulator, and makes an MTJ including the pinned layer and insulator and a magnetic domain in the magnetic thin wire in a first position to sandwich the insulator with pinned layer. First and second electrodes are at both ends of the magnetic thin wire. At least one third electrode is coupled to the magnetic thin wire between the first and second electrodes.

Abstract: A control circuit, on selecting a memory cell as a selected memory cell to perform a write operation, before executing the write operation, applies a first voltage to the selected memory cell via a first line and a second line to perform a first read operation. The control circuit, when judged that a result of the first read operation does not match write data intended to be written, executes the write operation. The control circuit, when judged that a result of the first read operation matches write data intended to be written, omits a voltage application operation for the write operation. The first voltage is larger than a second voltage which is applied to the selected memory cell via the first line and the second line in a second read operation, the second read operation acting as a normal read operation for reading held data of the memory cell.

Abstract: A magnetic memory device includes a magnetic thin wire including magnetic domains along a direction in which the magnetic thin wire extends. Magnetization directions of the magnetic domains are variable. A magnetic tunnel junction (MTJ) structure includes a pinned layer with a fixed magnetization direction and an insulator, and makes an MTJ including the pinned layer and insulator and a magnetic domain in the magnetic thin wire in a first position to sandwich the insulator with pinned layer. First and second electrodes are at both ends of the magnetic thin wire. At least one third electrode is coupled to the magnetic thin wire between the first and second electrodes.

Abstract: A control circuit, on selecting a memory cell as a selected memory cell to perform a write operation, before executing the write operation, applies a first voltage to the selected memory cell via a first line and a second line to perform a first read operation. The control circuit, when judged that a result of the first read operation does not match write data intended to be written, executes the write operation. The control circuit, when judged that a result of the first read operation matches write data intended to be written, omits a voltage application operation for the write operation. The first voltage is larger than a second voltage which is applied to the selected memory cell via the first line and the second line in a second read operation, the second read operation acting as a normal read operation for reading held data of the memory cell.

Abstract: A unit cell is composed of a memory cell transistor and a ferroelectric storage element connected in parallel between a source and a drain of the memory cell transistor. A memory cell block is composed of a plurality of unit cells connected in series. One end of the memory cell block is connected to a bit line via a block selecting transistor. The other end of the memory cell block is connected to a plate line. A redundancy unit cell is composed of a redundancy cell transistor and a ferroelectric storage element connected in parallel between a source and a drain of the redundancy cell transistor. A redundancy memory cell block is composed of a plurality of unit cells connected in series, the number of which is smaller than that of the unit cells in the memory cell block.

Abstract: A unit cell is composed of a memory cell transistor and a ferroelectric storage element connected in parallel between a source and a drain of the memory cell transistor. A memory cell block is composed of a plurality of unit cells connected in series. One end of the memory cell block is connected to a bit line via a block selecting transistor. The other end of the memory cell block is connected to a plate line. A redundancy unit cell is composed of a redundancy cell transistor and a ferroelectric storage element connected in parallel between a source and a drain of the redundancy cell transistor. A redundancy memory cell block is composed of a plurality of unit cells connected in series, the number of which is smaller than that of the unit cells in the memory cell block.