Patents by Inventor Sumiko Fujisaki
Sumiko Fujisaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11915939Abstract: A semiconductor fabricating method for a film to be processed containing a transition metal on an upper surface of a semiconductor wafer placed in a processing chamber in a container being etched with a gas for complexing the transition metal supplied into the processing chamber, including a first step of adsorbing, to the film, the complexing gas, while supplying the complexing gas, then increasing a temperature of the wafer to form an organic metal complex on a surface of the film, and volatilizing and desorbing the organic metal complex, and a second step of adsorbing, to the surface of the film, the complexing gas at a low temperature, while supplying the complexing gas, then stopping the supply of the complexing gas, and stepwise increasing the temperature of the wafer to volatilize and desorb an organic metal complex formed on the surface of the film.Type: GrantFiled: September 1, 2020Date of Patent: February 27, 2024Assignee: HITACHI HIGH-TECH CORPORATIONInventors: Yoshihide Yamaguchi, Sumiko Fujisaki
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Publication number: 20230005749Abstract: A semiconductor fabricating method for a film to be processed containing a transition metal on an upper surface of a semiconductor wafer placed in a processing chamber in a container being etched with a gas for complexing the transition metal supplied into the processing chamber, including a first step of adsorbing, to the film, the complexing gas, while supplying the complexing gas, then increasing a temperature of the wafer to form an organic metal complex on a surface of the film, and volatilizing and desorbing the organic metal complex, and a second step of adsorbing, to the surface of the film, the complexing gas at a low temperature, while supplying the complexing gas, then stopping the supply of the complexing gas, and stepwise increasing the temperature of the wafer to volatilize and desorb an organic metal complex formed on the surface of the film.Type: ApplicationFiled: September 1, 2020Publication date: January 5, 2023Inventors: Yoshihide Yamaguchi, Sumiko Fujisaki
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Patent number: 11515167Abstract: Provided is a plasma etching method which enables etching with high accuracy while controlling and reducing surface roughness of a transition metal film. The etching is performed for the transition metal film, which is formed on a sample and contains a transition metal element, by a first step of isotropically generating a layer of transition metal oxide on a surface of the transition metal film while a temperature of the sample is maintained at 100° C. or lower, a second step of raising the temperature of the sample to a predetermined temperature of 150° C. or higher and 250° C. or lower while a complexation gas is supplied to the layer of transition metal oxide, a third step of subliming and removing a reactant generated by an reaction between the complexation gas and the transition metal oxide formed in the first step while the temperature of the sample is maintained at 150° C. or higher and 250° C. or lower, and a fourth step of cooling the sample.Type: GrantFiled: February 1, 2019Date of Patent: November 29, 2022Assignee: HITACHI HIGH-TECH CORPORATIONInventors: Sumiko Fujisaki, Yoshihide Yamaguchi, Hiroyuki Kobayashi, Kazunori Shinoda, Kohei Kawamura, Yutaka Kouzuma, Masaru Izawa
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Patent number: 11380523Abstract: Provided is a semiconductor manufacturing apparatus that can etch a metal film containing a transition metal element at high speed and with high accuracy by using a complexing gas. The semiconductor manufacturing apparatus includes: a vacuum container 60; a processing chamber 1 that is provided in the vacuum container, and includes a stage 4 on which a sample 3 formed with a metal film containing a transition metal element is placed; and a vaporization chamber 2 that is provided in the vacuum container, and includes a vaporizing nozzle unit 70 configured to vaporize a complexing gas raw material liquid supplied from an outside. A complexing gas obtained by vaporizing the complexing gas raw material liquid is introduced into the processing chamber to etch the metal film of the sample.Type: GrantFiled: February 14, 2019Date of Patent: July 5, 2022Assignee: HITACHI HIGH-TECH CORPORATIONInventors: Yoshihide Yamaguchi, Sumiko Fujisaki
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Publication number: 20210358760Abstract: Provided is a plasma etching method which enables etching with high accuracy while controlling and reducing surface roughness of a transition metal film. The etching is performed for the transition metal film, which is formed on a sample and contains a transition metal element, by a first step of isotropically generating a layer of transition metal oxide on a surface of the transition metal film while a temperature of the sample is maintained at 100° C. or lower, a second step of raising the temperature of the sample to a predetermined temperature of 150° C. or higher and 250° C. or lower while a complexation gas is supplied to the layer of transition metal oxide, a third step of subliming and removing a reactant generated by an reaction between the complexation gas and the transition metal oxide formed in the first step while the temperature of the sample is maintained at 150° C. or higher and 250° C. or lower, and a fourth step of cooling the sample.Type: ApplicationFiled: February 1, 2019Publication date: November 18, 2021Inventors: Sumiko FUJISAKI, Yoshihide YAMAGUCHI, Hiroyuki KOBAYASHI, Kazunori SHINODA, Kohei KAWAMURA, Yutaka KOUZUMA, Masaru IZAWA
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Publication number: 20210233747Abstract: Provided is a semiconductor manufacturing apparatus that can etch a metal film containing a transition metal element at high speed and with high accuracy by using a complexing gas. The semiconductor manufacturing apparatus includes: a vacuum container 60; a processing chamber 1 that is provided in the vacuum container, and includes a stage 4 on which a sample 3 formed with a metal film containing a transition metal element is placed; and a vaporization chamber 2 that is provided in the vacuum container, and includes a vaporizing nozzle unit 70 configured to vaporize a complexing gas raw material liquid supplied from an outside. A complexing gas obtained by vaporizing the complexing gas raw material liquid is introduced into the processing chamber to etch the metal film of the sample.Type: ApplicationFiled: February 14, 2019Publication date: July 29, 2021Inventors: Yoshihide YAMAGUCHI, Sumiko FUJISAKI
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Patent number: 8050305Abstract: A semiconductor device having high reliability, a long lifetime and superior light emitting characteristics by applying a novel material to a p-type cladding layer is provided. A semiconductor device includes a p-type semiconductor layer on an InP substrate, in which the p-type semiconductor layer has a laminate structure formed by alternately laminating a first semiconductor layer mainly including Bex1Mgx2Znx3Te (0<x1<1, 0?x2<1, 0<x3<1, x1+x2+x3=1) and a second semiconductor layer mainly including Bex4Mgx5Znx6Te (0<x4<1, 0<x5<1, 0?x6<1, x4+x5+x6=1).Type: GrantFiled: June 3, 2008Date of Patent: November 1, 2011Assignees: Sony Corporation, Hitachi, Ltd., Sophia School CorporationInventors: Katsumi Kishino, Ichiro Nomura, Koshi Tamamura, Kunihiko Tasai, Tsunenori Asatsuma, Hitoshi Nakamura, Sumiko Fujisaki, Takeshi Kikawa
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Patent number: 7899104Abstract: An n-type cladding layer structure which has good luminescence properties without the use of substances corresponding to RoHS Directive and a high Cl-doping efficiency, i.e. which facilitates the manufacture of a semiconductor optical element and device with low crystal defects and high reliability, and an active layer and a p-type cladding layer therefor are provided. The n-type layer being lattice matched to an InP substrate and containing Group II-VI compound as a main ingredient is a Group II-VI compound semiconductor, in which the Group II elements consist of Mg, Zn, and Be and the Group VI elements consist of Se and Te. The n-type layer of the present invention is characterized by a large energy gap, high energy of the bottom of a conduction band that is effective for suppressing the Type II luminescence, high carrier concentration, and low crystal defects attributed to a good quality crystallinity.Type: GrantFiled: February 27, 2008Date of Patent: March 1, 2011Assignees: Hitachi, Ltd., Sophia School Corporation, Sony CorporationInventors: Katsumi Kishino, Ichiro Nomura, Tsunenori Asatsuma, Kunihiko Tasai, Koshi Tamamura, Hiroshi Nakajima, Hitoshi Nakamura, Sumiko Fujisaki, Takeshi Kikawa
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Patent number: 7668217Abstract: The present invention provides a Be-based group II-VI semiconductor laser using an InP substrate and having a stacked structure capable of continuous oscillation at a room temperature. A basic structure of a semiconductor laser is constituted by using a Be-containing lattice-matched II-VI semiconductor above an InP substrate. An active laser, an optical guide layer, and a cladding layer are constituted in a double hetero structure having a type I band line-up in order to enhance the injection efficiency of carriers to the active layer. Also, the active layer, the optical guide layer, and the cladding layer, which are capable of enhancing the optical confinement to the active layer, are constituted, and the cladding layer is constituted with bulk crystals.Type: GrantFiled: July 30, 2007Date of Patent: February 23, 2010Assignees: Hitachi, Ltd., Sophia School Corporation, Sony CorporationInventors: Katsumi Kishino, Ichiro Nomura, Tsunenori Asatsuma, Hitoshi Nakamura, Tsukuru Ohtoshi, Takeshi Kikawa, Sumiko Fujisaki, Shigehisa Tanaka
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Publication number: 20100040103Abstract: The present invention provides a semiconductor device including: a semiconductor layer including an n-type first cladding layer, an n-type second cladding layer, an active layer, a p-type first cladding layer, and a p-type second cladding layer in this order on an InP substrate. The n-type first cladding layer and the n-type second cladding layer satisfy formulas (1) to (4) below, or the p-type first cladding layer and the p-type second cladding layer satisfy formulas (5) to (8) below.Type: ApplicationFiled: August 5, 2009Publication date: February 18, 2010Applicants: HITACHI, LTD, SOPHIA SCHOOL CORPORATION, SONY CORPORATIONInventors: Katsumi Kishino, Ichiro Nomura, Koshi Tamamura, Kunihiko Tasai, Tsunenori Asatsuma, Hiroshi Nakajima, Hitoshi Nakamura, Sumiko Fujisaki, Takeshi Kikawa
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Publication number: 20090141763Abstract: There is disclosed a Be-containing II-VI group semiconductor laser that has a laminated structure formed on an InP substrate to continuously emit at room temperature without crystal degradation. A basic structure of the semiconductor laser is formed over the InP substrate by use of a lattice-matched II-VI group semiconductor including Be. An active layer and cladding layers are formed to be a double heterostructure with a type I band lineup, in order to increase the efficiency for injecting carriers into the active layer. The active layer and the cladding layers are also formed to enhance the light confinement to the active layer, in which the Mg composition of the p-type cladding layer is set to Mg<0.2.Type: ApplicationFiled: February 27, 2008Publication date: June 4, 2009Inventors: Katsumi Kishino, Ichiro Nomura, Tsunenori Asatsuma, Sumiko Fujisaki, Hitoshi Nakamura, Takeshi Kikawa, Shigehisa Tanaka
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Publication number: 20090059985Abstract: An n-type cladding layer structure which has good luminescence properties without the use of substances corresponding to RoHS Directive and a high Cl-doping efficiency, i.e. which facilitates the manufacture of a semiconductor optical element and device with low crystal defects and high reliability, and an active layer and a p-type cladding layer therefor are provided. The n-type layer being lattice matched to an InP substrate and containing Group II-VI compound as a main ingredient is a Group II-VI compound semiconductor, in which the Group II elements consist of Mg, Zn, and Be and the Group VI elements consist of Se and Te. The n-type layer of the present invention is characterized by a large energy gap, high energy of the bottom of a conduction band that is effective for suppress the Type II luminescence, high carrier concentration, and low crystal defects attributed to a good quality crystallinity.Type: ApplicationFiled: February 27, 2008Publication date: March 5, 2009Inventors: Katsumi Kishino, Ichiro Nomura, Tsunenori Asatsuma, Kunihiko Tasai, Koshi Tamamura, Hiroshi Nakajima, Hitoshi Nakamura, Sumiko Fujisaki, Takeshi Kikawa
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Publication number: 20080298415Abstract: A semiconductor device having high reliability, a long lifetime and superior light emitting characteristics by applying a novel material to a p-type cladding layer is provided. A semiconductor device includes a p-type semiconductor layer on an InP substrate, in which the p-type semiconductor layer has a laminate structure formed by alternately laminating a first semiconductor layer mainly including Bex1Mgx2Znx3Te (0<x1<1, 0<x2<1, 0<x3<1, x1+x2+x3=1) and a second semiconductor layer mainly including Bex4Mgx5Znx6Te (0<x4<1, 0<x5<1, 0<x6<1, x4+x5+x6=1).Type: ApplicationFiled: June 3, 2008Publication date: December 4, 2008Applicants: SONY CORPORATION, HITACHI, LTD, SOPHIA SCHOOL CORPORATIONInventors: Katsumi Kishino, Ichiro Nomura, Koshi Tamamura, Kunihiko Tasai, Tsunenori Asatsuma, Hitoshi Nakamura, Sumiko Fujisaki, Takeshi Kikawa
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Patent number: 7422919Abstract: An avalanche photodiode includes at least one crystal layer having a larger band-gap than that of an absorption layer formed by a composition or material different from that of the absorption layer formed on a junction interface between a compound semiconductor absorbing an optical signal and an Si multiplication layer, and the crystal layer may be intentionally doped with n or p type impurities to cancel electrical influences of the impurities containing oxides present on the junction interface of compound semiconductor and surface of Si.Type: GrantFiled: December 30, 2005Date of Patent: September 9, 2008Assignees: Hitachi, Ltd., Opnext Japan, Inc.Inventors: Shigehisa Tanaka, Sumiko Fujisaki, Yasunobu Matsuoka
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Publication number: 20080049803Abstract: The present invention provides a Be-based group II-VI semiconductor laser using an InP substrate and having a stacked structure capable of continuous oscillation at a room temperature. A basic structure of a semiconductor laser is constituted by using a Be-containing lattice-matched II-VI semiconductor above an InP substrate. An active laser, an optical guide layer, and a cladding layer are constituted in a double hetero structure having a type I band line-up in order to enhance the injection efficiency of carriers to the active layer. Also, the active layer, the optical guide layer, and the cladding layer, which are capable of enhancing the optical confinement to the active layer, are constituted, and the cladding layer is constituted with bulk crystals.Type: ApplicationFiled: July 30, 2007Publication date: February 28, 2008Inventors: Katsumi Kishino, Ichiro Nomura, Tsunenori Asatsuma, Hitoshi Nakamura, Tsukuru Ohtoshi, Takeshi Kikawa, Sumiko Fujisaki, Shigehisa Tanaka
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Publication number: 20060110841Abstract: An avalanche photodiode includes at least one crystal layer having a larger band-gap than that of an absorption layer formed by a composition or material different from that of the absorption layer formed on a junction interface between a compound semiconductor absorbing an optical signal and an Si multiplication layer, and the crystal layer may be intentionally doped with n or p type impurities to cancel electrical influences of the impurities containing oxides present on the junction interface of compound semiconductor and surface of Si.Type: ApplicationFiled: December 30, 2005Publication date: May 25, 2006Inventors: Shigehisa Tanaka, Sumiko Fujisaki, Yasunobu Matsuoka
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Publication number: 20050006678Abstract: An avalanche photodiode includes at least one crystal layer having a larger band-gap than that of an absorption layer formed by a composition or material different from that of the absorption layer formed on a junction interface between a compound semiconductor absorbing an optical signal and an Si multiplication layer, and the crystal layer may be intentionally doped with n or p type impurities to cancel electrical influences of the impurities containing oxides present on the junction interface of compound semiconductor and surface of Si.Type: ApplicationFiled: January 26, 2004Publication date: January 13, 2005Inventors: Shigehisa Tanaka, Sumiko Fujisaki, Yasunobu Matsuoka
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Patent number: 6800914Abstract: Reducing a dark current in a semiconductor photodetector provided with a second mesa including an regrown layer around a first mesa. An n-type buffer layer, a n-type multiplication layer, a p-type field control layer, a p-type absorption layer, a cap layer made of p-type InAlAs crystal, and a p-type contact layer 107 are made to grow on a main surface of a n-type substrate. Thereafter the p-type contact layer, the p-type cap layer, the p-type absorption layer and the p-type field control layer are patterned to form a first mesa. Next, after making a p-type regrown layer selectively grow around the first mesa or by forming a groove in the regrow layer located in a vicinity of the p-type cap type during a step of the selective growth, the p-type cap layer containing Al and the regrow layer are separated owing to the groove such that no current path is formed between both layers.Type: GrantFiled: August 19, 2002Date of Patent: October 5, 2004Assignee: Opnext Japan, Inc.Inventors: Kazuhiro Ito, Shigehisa Tanaka, Sumiko Fujisaki, Yasunobu Matsuoka, Takashi Toyonaka
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Publication number: 20030218226Abstract: Reducing a dark current in a semiconductor photodetector provided with a second mesa including an regrown layer around a first mesa. An n-type buffer layer, a n-type multiplication layer, a p-type field control layer, a p-type absorption layer, a cap layer made of p-type InAlAs crystal, and a p-type contact layer 107 are made to grow on a main surface of a n-type substrate. Thereafter the p-type contact layer, the p-type cap layer, the p-type absorption layer and the p-type field control layer are patterned to form a first mesa. Next, after making a p-type regrown layer selectively grow around the first mesa or by forming a groove in the regrow layer located in a vicinity of the p-type cap type during a step of the selective growth, the p-type cap layer containing Al and the regrow layer are separated owing to the groove such that no current path is formed between both layers.Type: ApplicationFiled: August 19, 2002Publication date: November 27, 2003Applicant: OpNext Japan, Inc.Inventors: Kazuhiro Ito, Shigehisa Tanaka, Sumiko Fujisaki, Yasunobu Matsuoka, Takashi Toyonaka
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Patent number: 6635908Abstract: The object of disclosing the novel art consists in providing a highly reliable mesa-structured avalanche photo-diode using a novel structure capable of keeping the dark current low, and a fabrication method thereof. The avalanche photo-diode for achieving the object has an absorption layer for absorbing light to generate a carrier, a multiplication layer for multiplying the generated carrier, and a field control layer inserted between the absorption layer and the multiplication layer. Moreover, a first mesa including at least part of the multiplication layer and part of the field control layer is formed over a substrate, a second mesa including another part of the field control layer and the absorption layer is formed over the first mesa, the area of the top surface of the first mesa is greater than that of the bottom surface of the second mesa, and a semiconductor layer is formed over the part of the first mesa top surface not covered by the second mesa and the side surface of the second mesa.Type: GrantFiled: August 31, 2001Date of Patent: October 21, 2003Assignee: Hitachi, Ltd.Inventors: Shigehisa Tanaka, Yasunobu Matsuoka, Kazuhiro Ito, Tomohiro Ohno, Sumiko Fujisaki, Akira Taike, Tsukuru Ohtoshi, Shinji Tsuji