Patents by Inventor Sumiko Maeda

Sumiko Maeda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Logic verification device, logic verification method and logic verification computer program
    Patent number: 7131086
    Abstract: A logic verification device, a logic verification method and a logic verification computer program that can reduce the number of steps involved in designing a logic circuit particularly when the designed logic circuit is subjected to logic verification and modification at the spot where an error is detected.
    Type: Grant
    Filed: August 11, 2004
    Date of Patent: October 31, 2006
    Assignee: Fujitsu Limited
    Inventors: Junya Yamasaki, Sumiko Maeda, Kenya Takeyama, Yukio Makino
  • Logic verification device, logic verification method and logic verification computer program
    Publication number: 20050229122
    Abstract: A logic verification device, a logic verification method and a logic verification computer program that can reduce the number of steps involved in designing a logic circuit particularly when the designed logic circuit is subjected to logic verification and modification at the spot where an error is detected.
    Type: Application
    Filed: August 11, 2004
    Publication date: October 13, 2005
    Applicant: Fujitsu Limited
    Inventors: Junya Yamasaki, Sumiko Maeda, Kenya Takeyama, Yukio Makino
  • Method for making electronic circuit design data and CAD system using the method
    Patent number: 5856925
    Abstract: In a method for managing design data regarding an electronic circuit in order to design and analyze the electronic circuit, the design data is arranged according to a hierarchical-layer module structure. The design data in each of hierarchical layers of the hierarchical-layer module structure is divided into objects. The objects together for each of the hierarchical layers are connected together and the objects are connected together over the hierarchical layers. The design data including design data having different items and design data having different data lengths is integrally managed.
    Type: Grant
    Filed: June 5, 1997
    Date of Patent: January 5, 1999
    Assignee: Fujitsu Limited
    Inventors: Sumiko Maeda, Hisataka Fukase