Abstract: Shift code patterns at four continuous phases obtained by dividing 15 shift code patterns given to the respective flip-flops of a linear feedback shift register of degree 4 into four parts are stored in a code memory (11). Besides, mask code patterns to shift a phase of a PN code (PN) to be generated by every four phases, are stored in a code mask memory (12). Next, a logical operation is performed at a phase shift circuit (13) by using the shift code pattern outputted from the code memory (11) and the mask code pattern outputted from the code mask memory (12), to generate a PN code (PN) having a code length of 15 from a random phase.

Abstract: Shift code patterns at four continuous phases obtained by dividing 15 shift code patterns given to the respective flip-flops of a linear feedback shift register of degree 4 into four parts are stored in a code memory (11). Besides, mask code patterns to shift a phase of a PN code (PN) to be generated by every four phases, are stored in a code mask memory (12). Next, a logical operation is performed at a phase shift circuit (13) by using the shift code pattern outputted from the code memory (11) and the mask code pattern outputted from the code mask memory (12), to generate a PN code (PN) having a code length of 15 from a random phase.