Patents by Inventor Sumin NOH

Sumin NOH has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240201256
    Abstract: A device is provided. The device includes: a plurality of physically unclonable function (PUF) cells, each of the plurality of PUF cells including at least one logic gate and being configured to generate an output signal based on at least one threshold level of the at least one logic gate; a signal generator configured to generate an input signal that is provided to each of the plurality of PUF cells; and a controller configured to, in a test mode, generate a control signal to control the signal generator to vary the input signal to control the plurality of PUF cells to output a plurality of output signals according to the input signal, and identify at least one weak PUF cell from among the plurality of PUF cells based on the output signal generated by the at least one weak PUF cell being an unstable output signal. The controller is further configured to disconnect the plurality of PUF cells from the signal generator in a normal mode.
    Type: Application
    Filed: December 13, 2023
    Publication date: June 20, 2024
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sumin Noh, Yongki Lee, Jieun Park, Yunhyeok Choi, Bohdan Karpinskyy
  • Publication number: 20230153069
    Abstract: A random number generator according to example embodiments includes an initial random number generator configured to generate an initial random number, a self-timed ring (STR) oscillator configured to receive the initial random number, the STR oscillator having a plurality of ring stages generating, in response to a clock, either a bubble that does not change an output state of a previous clock or a token changing the output state of the previous clock, a duty corrector configured to adjust a duty of each of output values of the ring stages, and a sampling circuit configured to sample a random number using a logic operation from the duty-corrected output values.
    Type: Application
    Filed: September 14, 2022
    Publication date: May 18, 2023
    Inventors: Jieun Park, Yongki Lee, Sumin Noh, Yunhyeok Choi, Bohdan Karpinskyy
  • Publication number: 20230025153
    Abstract: A random number generating circuit includes: an oscillation circuit including a plurality of first delay elements connected to each other in series to generate an oscillation signal; a sampling circuit including a plurality of second delay elements connected to each other in series to generate a plurality of sampling signals by sampling the oscillation signal at a plurality of sampling points in time based on the plurality of second delay elements; and a random number determining circuit configured to generate a random number based on a target sampling point in time associated with a target sampling signal in which a first logic level transition occurs from among the plurality of sampling signals, wherein the plurality of sampling points includes the target sampling point.
    Type: Application
    Filed: July 18, 2022
    Publication date: January 26, 2023
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yunhyeok CHOI, Yongki LEE, Sumin NOH, Jieun PARK, Bohdan KARPINSKYY