Abstract: A semiconductor device includes: a first metal layer including a gate electrode; a first insulating layer provided on the first metal layer; an oxide semiconductor layer provided on the first insulating layer; a second insulating layer provided on the oxide semiconductor layer; a second metal layer provided on the oxide semiconductor layer and the second insulating layer, the second metal layer including a source electrode; a third insulating layer provided on the second metal layer; and a first transparent electrode layer provided on the third insulating layer. The oxide semiconductor layer includes a first portion lying above the gate electrode and a second portion extending from the first portion so as to lie across an edge of the gate electrode on the drain electrode side. The third insulating layer does not include an organic insulating layer.

Abstract: A semiconductor device (100A) includes a thin film transistor (10), an inter-layer insulation layer (22) covering the thin film transistor, and a transparent conductive layer (24) formed on the inter-layer insulation layer. The metal oxide layer (16) of the thin film transistor includes a first portion (16a) overlapping the gate electrode (12) via a gate insulation layer (14) and a second portion (16b) not overlapping the gate electrode (12). The second portion (16b) crosses a different edge (e2) different from an edge (e1) of the drain electrode (18d) on a side of the first portion when viewed in the normal direction of the substrate (11). The inter-layer insulation layer has a contact hole (22a) disposed to overlap a part of the drain electrode (18d) and at least a part of the second portion (16b) of the metal oxide layer when viewed in the normal direction of the substrate.

Abstract: A semiconductor device includes a TFT (101), the TFT including a gate electrode (12), a gate insulating layer (14) covering the gate electrode, a metal oxide layer (16A) including a channel region (16c), a source contact region (16s) and a drain contact region (16d), a first electrode (18A) in contact with the source contact region, an insulating layer (22) formed on the metal oxide layer and the first electrode, the insulating layer having a first opening (22p) therein through which a portion of the metal oxide layer is exposed, and a light-transmissive second electrode (24) formed on the insulating layer and in a contact hole including the first opening, wherein the second electrode (24) is in contact with the drain contact region (16d) in the contact hole, the drain contact region (16d) is a portion of a region (17) of the metal oxide layer (16A) that is exposed through the contact hole, and as seen from a direction normal to a substrate (11), the second electrode (24) does not overlap the channel region (

Abstract: A semiconductor device includes: a first metal layer including a gate electrode; a first insulating layer provided on the first metal layer; an oxide semiconductor layer provided on the first insulating layer; a second insulating layer provided on the oxide semiconductor layer; a second metal layer provided on the oxide semiconductor layer and the second insulating layer, the second metal layer including a source electrode; a third insulating layer provided on the second metal layer; and a first transparent electrode layer provided on the third insulating layer. The oxide semiconductor layer includes a first portion lying above the gate electrode and a second portion extending from the first portion so as to lie across an edge of the gate electrode on the drain electrode side. The third insulating layer does not include an organic insulating layer.

Abstract: A semiconductor device (100A) includes a thin film transistor (10), an inter-layer insulation layer (22) covering the thin film transistor, and a transparent conductive layer (24) formed on the inter-layer insulation layer. The metal oxide layer (16) of the thin film transistor includes a first portion (16a) overlapping the gate electrode (12) via a gate insulation layer (14) and a second portion (16b) not overlapping the gate electrode (12). The second portion (16b) crosses a different edge (e2) different from an edge (e1) of the drain electrode (18d) on a side of the first portion when viewed in the normal direction of the substrate (11). The inter-layer insulation layer has a contact hole (22a) disposed to overlap a part of the drain electrode (18d) and at least a part of the second portion (16b) of the metal oxide layer when viewed in the normal direction of the substrate.

Abstract: A semiconductor device includes: a first metal layer including a gate electrode; a first insulating layer provided on the first metal layer; an oxide semiconductor layer provided on the first insulating layer; a second insulating layer provided on the oxide semiconductor layer; a second metal layer provided on the oxide semiconductor layer and the second insulating layer, the second metal layer including a source electrode; a third insulating layer provided on the second metal layer; and a first transparent electrode layer provided on the third insulating layer. The oxide semiconductor layer includes a first portion lying above the gate electrode and a second portion extending from the first portion so as to lie across an edge of the gate electrode on the drain electrode side. The third insulating layer does not include an organic insulating layer.

Abstract: A semiconductor device includes a TFT (101), the TFT including a gate electrode (12), a gate insulating layer (14) covering the gate electrode, a metal oxide layer (16A) including a channel region (16c), a source contact region (16s) and a drain contact region (16d), a first electrode (18A) in contact with the source contact region, an insulating layer (22) formed on the metal oxide layer and the first electrode, the insulating layer having a first opening (22p) therein through which a portion of the metal oxide layer is exposed, and a light-transmissive second electrode (24) formed on the insulating layer and in a contact hole including the first opening, wherein the second electrode (24) is in contact with the drain contact region (16d) in the contact hole, the drain contact region (16d) is a portion of a region (17) of the metal oxide layer (16A) that is exposed through the contact hole, and as seen from a direction normal to a substrate (11), the second electrode (24) does not overlap the channel region (

Abstract: A semiconductor device (1001) includes: a memory cell; and a writing control circuit (107), wherein the memory cell includes a memory transistor (10A) which has an active layer (7A), the active layer (7A) including a metal oxide, the memory transistor (10A) is a transistor which is capable of being irreversibly changed from a semiconductor state where a drain current Ids depends on a gate-source voltage Vgs to a resistor state where the drain current Ids does not depend on the gate-source voltage Vgs, and the writing control circuit (107) is configured to control voltages applied to a drain electrode, a source electrode and a gate electrode such that Vgs?Vds+Vth is satisfied where Vth is a threshold voltage of the memory transistor (10A) and Vds is a drain-source voltage of the memory transistor (10A), whereby writing in the memory transistor (10A) is performed.

Abstract: A semiconductor device (1001) includes: a first transistor (10A) having a first channel length L1 and a first channel width W1; and a second transistor (10B) having a second channel length L2 and a second channel width W2, wherein the first transistor (10A) and the second transistor (10B) include an active layer formed from a common oxide semiconductor film, the first transistor (10A) is a memory transistor which is capable of being irreversibly changed from a semiconductor state where a drain current Isd depends on a gate voltage Vg to a resistor state where the drain current Isd does not depend on the gate voltage Vg, and the first channel length L1 is smaller than the second channel length L2.

Abstract: A semiconductor device includes: a first metal layer including a gate electrode; a first insulating layer provided on the first metal layer; an oxide semiconductor layer provided on the first insulating layer; a second insulating layer provided on the oxide semiconductor layer; a second metal layer provided on the oxide semiconductor layer and the second insulating layer, the second metal layer including a source electrode; a third insulating layer provided on the second metal layer; and a first transparent electrode layer provided on the third insulating layer. The oxide semiconductor layer includes a first portion lying above the gate electrode and a second portion extending from the first portion so as to lie across an edge of the gate electrode on the drain electrode side. The third insulating layer does not include an organic insulating layer.

Abstract: A semiconductor device includes a memory transistor (10A) which is capable of being irreversibly changed from a semiconductor state where drain current Ids depends on gate voltage Vg to a resistor state where drain current Ids does not depend on gate voltage Vg. The memory transistor (10A) includes a gate electrode (3), a metal oxide layer (7), a gate insulating film (5), and source and drain electrodes. The drain electrode (9d) has a multilayer structure which includes a first drain metal layer (9d1) and a second drain metal layer (9d2), the first drain metal layer (9d1) being made of a first metal whose melting point is not less than 1200° C., the second drain metal layer (9d2) being made of a second metal whose melting point is lower than that of the first metal. Part P of the drain electrode 9d extends over both the metal oxide layer (7) and the gate electrode (3) when viewed in a direction normal to a surface of the substrate.

Abstract: A semiconductor device (100A) includes a first metal layer (12) including a gate electrode (12g); a gate insulating layer (14) formed on the first metal layer; an oxide semiconductor layer (16) formed on the gate insulating layer; a second metal layer (18) formed on the oxide semiconductor layer; an interlayer insulating layer (22) formed on the second metal layer; and a transparent electrode layer (TE) including a transparent conductive layer (Tc). The oxide semiconductor layer includes a first portion (16a) and a second portion (16b) extending while crossing an edge of the gate electrode. The second metal layer includes a source electrode (18s) and a drain electrode (18d). The interlayer insulating layer does not include an organic insulating layer. The interlayer insulating layer includes a contact hole (22a) formed so as to overlap the second portion and an end of the drain electrode that is closer to the second portion.

Abstract: A semiconductor device (1001) includes: a memory cell; and a writing control circuit (107), wherein the memory cell includes a memory transistor (10A) which has an active layer (7A), the active layer (7A) including a metal oxide, the memory transistor (10A) is a transistor which is capable of being irreversibly changed from a semiconductor state where a drain current Ids depends on a gate-source voltage Vgs to a resistor state where the drain current Ids does not depend on the gate-source voltage Vgs, and the writing control circuit (107) is configured to control voltages applied to a drain electrode, a source electrode and a gate electrode such that Vgs?Vds+Vth is satisfied where Vth is a threshold voltage of the memory transistor (10A) and Vds is a drain-source voltage of the memory transistor (10A), whereby writing in the memory transistor (10A) is performed.

Abstract: A memory cell (101) includes a memory transistor (10A) having channel length L1 and channel width W1, and a plurality of select transistors (10B) each electrically being connected in series with the memory transistor and independently having channel length L2 and channel width W2, wherein each of the memory transistor and the plurality of select transistors includes an active layer (7A) formed from a common oxide semiconductor film, the memory transistor is a transistor which is capable of being irreversibly changed from a semiconductor state where drain current Ids depends on gate voltage Vg to a resistor state where drain current Ids does not depend on gate voltage Vg, and channel length L2 is greater than channel length L1.

Abstract: A semiconductor device includes a memory transistor (10A) which is capable of being irreversibly changed from a semiconductor state where drain current Ids depends on gate voltage Vg to a resistor state where drain current Ids does not depend on gate voltage Vg. The memory transistor (10A) includes a gate electrode (3), a metal oxide layer (7), a gate insulating film (5), and source and drain electrodes. The drain electrode (9d) has a multilayer structure which includes a first drain metal layer (9d1) and a second drain metal layer (9d2), the first drain metal layer (9d1) being made of a first metal whose melting point is not less than 1200° C., the second drain metal layer (9d2) being made of a second metal whose melting point is lower than that of the first metal. Part P of the drain electrode 9d extends over both the metal oxide layer (7) and the gate electrode (3) when viewed in a direction normal to a surface of the substrate.

Abstract: A semiconductor device (1001) includes: a first transistor (10A) having a first channel length L1 and a first channel width W1; and a second transistor (10B) having a second channel length L2 and a second channel width W2, wherein the first transistor (10A) and the second transistor (10B) include an active layer formed from a common oxide semiconductor film, the first transistor (10A) is a memory transistor which is capable of being irreversibly changed from a semiconductor state where a drain current Isd depends on a gate voltage Vg to a resistor state where the drain current Isd does not depend on the gate voltage Vg, and the first channel length L1 is smaller than the second channel length L2.

Abstract: A memory cell (101) includes a memory transistor (10A) having channel length L1 and channel width W1, and a plurality of select transistors (10B) each electrically being connected in series with the memory transistor and independently having channel length L2 and channel width W2, wherein each of the memory transistor and the plurality of select transistors includes an active layer (7A) formed from a common oxide semiconductor film, the memory transistor is a transistor which is capable of being irreversibly changed from a semiconductor state where drain current Ids depends on gate voltage Vg to a resistor state where drain current Ids does not depend on gate voltage Vg, and channel length L2 is greater than channel length L1.

Abstract: A semiconductor device (100A) includes a first metal layer (12) including a gate electrode (12g); a gate insulating layer (14) formed on the first metal layer; an oxide semiconductor layer (16) formed on the gate insulating layer; a second metal layer (18) formed on the oxide semiconductor layer; an interlayer insulating layer (22) formed on the second metal layer; and a transparent electrode layer (TE) including a transparent conductive layer (Tc). The oxide semiconductor layer includes a first portion (16a) and a second portion (16b) extending while crossing an edge of the gate electrode. The second metal layer includes a source electrode (18s) and a drain electrode (18d). The interlayer insulating layer does not include an organic insulating layer. The interlayer insulating layer includes a contact hole (22a) formed so as to overlap the second portion and an end of the drain electrode that is closer to the second portion.

Abstract: The present invention provides a non-volatile memory device using a memory transistor including an oxide semiconductor, capable of writing with low power consumption, without receiving an influence of deterioration of a selection transistor connected in series to the memory transistor. A memory cell 1 includes a memory transistor Qm, and first and second selection transistors Q1 and Q2. During a writing operation, the memory transistor Qm and the first selection transistor Q1 are set to the ON state, and the second selection transistor Q2 is set to the OFF state. A writing current is flown to a series circuit of the memory transistor Qm and the first selection transistor Q1. The memory transistor Qm is transited from a first state that indicates a transistor characteristic to a second state that indicates an ohmic resistance characteristic.

Abstract: The invention provides a thin film transistor that can reduce an off-current flowing in end-parts in a channel width direction of a channel layer and a manufacturing method therefor.