Patents by Inventor Sumio Kawakami

Sumio Kawakami has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5177568
    Abstract: A tunnel injection type semiconductor device having an MIS structure comprising a semiconductor region, a source, a drain and a gate electrode, wherein said source and said drain are composed of a metal or metal compound member, respectively, and wherein both have an overlapping portion with said gate electrode. A first conductivity type high impurity concentration semiconductor layer is formed in said semiconductor region in contact with and contiguous to said metalic member at the drain side. The source provides a Schottky barrier junction to said semiconductor region while said drain provides an ohmic contact to said semiconductor region. Using this structure a tunneling current flowing across a Schottky barrier junction between said source and said drain is controlled by a gate voltage.
    Type: Grant
    Filed: July 30, 1991
    Date of Patent: January 5, 1993
    Assignee: Hitachi, Ltd.
    Inventors: Hideo Honma, Sumio Kawakami, Takahiro Nagano
  • Patent number: 4083062
    Abstract: An avalanche photodiode has a rectification barrier formed by an n.sup.+ -layer and a p-type layer of a low doping concentration. A thin p-layer having a higher doping concentration than a p.sup.- -layer is inserted between the p.sup.- -layer and a .pi.-layer, whereby the avalanche breakdown voltage of the photodiode is lowered considerably.
    Type: Grant
    Filed: February 8, 1977
    Date of Patent: April 4, 1978
    Assignee: Hitachi, Ltd.
    Inventors: Hirobumi Ohuchi, Sumio Kawakami, Masahiro Okamura
  • Patent number: 4079405
    Abstract: A semiconductor photodetector comprising a first semiconductor layer having N-type conductivity; a second semiconductor layer having N-type conductivity, disposed in the vicinity of the first semiconductor layer and having a resistivity higher than that of the first semiconductor layer; a third region having P-type conductivity, disposed in the vicinity of the second semiconductor layer and having a thickness smaller than that of the second semiconductor layer; a first main electrode kept in ohmic contact with the first semiconductor layer; and a second main electrode kept in ohmic contact with a portion of the third region, the surface of the third region serving as a light receiving surface.
    Type: Grant
    Filed: June 24, 1975
    Date of Patent: March 14, 1978
    Assignee: Hitachi, Ltd.
    Inventors: Hirobumi Ohuchi, Masahiro Okamura, Sumio Kawakami, Takuzo Ogawa