Abstract: A through-hole electrode substrate includes a substrate including a through-hole extending from a first aperture of a first surface to a second aperture of a second surface, an area of the second aperture being larger than that of the first aperture, the through-hole having a minimum aperture part between the first aperture and the second aperture, wherein an area of the minimum aperture part in a planer view is smallest among a plurality of areas of the through-hole in a planer view, a filler arranged within the through-hole, and at least one gas discharge member contacting the filler exposed to one of the first surface and the second surface.

Abstract: A through-hole electrode substrate includes a substrate including a through-hole extending from a first aperture of a first surface to a second aperture of a second surface, an area of the second aperture being larger than that of the first aperture, the through-hole having a minimum aperture part between the first aperture and the second aperture, wherein an area of the minimum aperture part in a planer view is smallest among a plurality of areas of the through-hole in a planer view, a filler arranged within the through-hole, and at least one gas discharge member contacting the filler exposed to one of the first surface and the second surface.

Abstract: A through-hole electrode substrate includes a substrate including a through-hole extending from a first aperture of a first surface to a second aperture of a second surface, an area of the second aperture being larger than that of the first aperture, the through-hole having a minimum aperture part between the first aperture and the second aperture, wherein an area of the minimum aperture part in a planer view is smallest among a plurality of areas of the through-hole in a planer view, a filler arranged within the through-hole, and at least one gas discharge member contacting the filler exposed to one of the first surface and the second surface.

Abstract: A through-hole electrode substrate includes a substrate including a through-hole extending from a first aperture of a first surface to a second aperture of a second surface, an area of the second aperture being larger than that of the first aperture, the through-hole having a minimum aperture part between the first aperture and the second aperture, wherein an area of the minimum aperture part in a planer view is smallest among a plurality of areas of the through-hole in a planer view, a filler arranged within the through-hole, and at least one gas discharge member contacting the filler exposed to one of the first surface and the second surface.

Abstract: A through-hole electrode substrate includes a substrate including a through-hole extending from a first aperture of a first surface to a second aperture of a second surface, an area of the second aperture being larger than that of the first aperture, the through-hole having a minimum aperture part between the first aperture and the second aperture, wherein an area of the minimum aperture part in a planer view is smallest among a plurality of areas of the through-hole in a planer view, a filler arranged within the through-hole, and at least one gas discharge member contacting the filler exposed to one of the first surface and the second surface.

Abstract: A through-hole electrode substrate includes a substrate including a through-hole extending from a first aperture of a first surface to a second aperture of a second surface, an area of the second aperture being larger than that of the first aperture, the through-hole having a minimum aperture part between the first aperture and the second aperture, wherein an area of the minimum aperture part in a planer view is smallest among a plurality of areas of the through-hole in a planer view, a filler arranged within the through-hole, and at least one gas discharge member contacting the filler exposed to one of the first surface and the second surface.

Abstract: A through-hole electrode substrate includes a substrate including a through-hole extending from a first aperture of a first surface to a second aperture of a second surface, an area of the second aperture being larger than that of the first aperture, the through-hole having a minimum aperture part between the first aperture and the second aperture, wherein an area of the minimum aperture part in a planer view is smallest among a plurality of areas of the through-hole in a planer view, a filler arranged within the through-hole, and at least one gas discharge member contacting the filler exposed to one of the first surface and the second surface.

Abstract: A through-hole electrode substrate includes a substrate including a through-hole extending from a first aperture of a first surface to a second aperture of a second surface, an area of the second aperture 5 being larger than that of the first aperture, the through-hole having a minimum aperture part between the first aperture and the second aperture, wherein an area of the minimum aperture part in a planar view is smallest among a plurality of areas of the through-hole in a planar view, a filler arranged within the 10 through-hole, and at least one gas discharge member contacting the filler exposed to one of the first surface and the second surface.

Abstract: A through-hole electrode substrate includes a substrate including a through-hole extending from a first aperture of a first surface to a second aperture of a second surface, an area of the second aperture being larger than that of the first aperture, the through-hole having a minimum aperture part between the first aperture and the second aperture, wherein an area of the minimum aperture part in a planer view is smallest among a plurality of areas of the through-hole in a planer view, a filler arranged within the through-hole, and at least one gas discharge member contacting the filler exposed to one of the first surface and the second surface.

Abstract: A semiconductor device has a semiconductor circuit provided on a semiconductor substrate. The semiconductor circuit has a source, a drain, a gate and a wiring connected to one of the source, the drain and the gate. Conductors for electrostatic discharge protection are connected to one of a ground line and a power supply line and are disposed over a region of the semiconductor circuit not occupied by the wiring. A ratio of a total area of the conductors disposed over the semiconductor circuit to an area of a chip occupied by the semiconductor circuit is 40% or more.

Abstract: Provided is a semiconductor electrostatic discharge protection device with a high tolerance for an electrostatic discharge without increase in manufacturing cost and degradation in performance of a semiconductor device. Conductors are arranged over a semiconductor circuit formed on a semiconductor substrate, a part of the conductors are connected to a power supply line, and the rest of the conductors are connected to a ground line, in order to enhance the tolerance for the electrostatic discharge in an air discharge model. Further, an areal ratio of the conductors with respect to the semiconductor circuit is set at 40% or more, thereby forming a semiconductor electrostatic discharge protection device with excellent efficiency.

Abstract: A photodiode comprises an optical detection portion for detecting an optical signal and outputting a photoelectric conversion signal. The optical detection portion has a semiconductor substrate of a first conductive type and semiconductor layers of a second conductive type formed in spaced-apart relation in a surface of the semiconductor subtrate. A depletion layer is formed in the semiconductor subtrate by application of a reverse bias to the photodiode so as to surround the semiconductor layers. An etched surface portion of the depletion layer is disposed between the semiconductor layers so that an interface level region of the surface of the semiconductor substrate does not exist between the semiconductor layers.

Abstract: Provided is a manufacturing method for realizing a low cost and high performance vertical MOSFET. The vertical MOSFET manufacturing method of the present invention gives the portion formed between the trench and the semiconductor substrate flat portion a smooth shape by doping the semiconductor substrate with an impurity through ion implantation and then thermally oxidizing the substrate. The withstand voltage of the gate insulating film is thus improved. Furthermore, the semiconductor device manufacturing method of the present invention puts the formation of the N+ diffusion layer serving as a source after the formation of the trench and the subsequent formation of the gate electrode in the trench, and therefore can avoid re-diffusion of the N+ diffusion layer, which otherwise causes an increase in leak current.

Abstract: In a power management semiconductor device or analog semiconductor device having a CMOS and a resistor, a conductivity type of a gate electrode of the CMOS is P-type as to both an NMOS and a PMOS, a short channel and a low threshold voltage are possible since an E-type PMOS is surface channel type, the short channel and the low threshold voltage are possible since a buried channel type NMOS is extremely shallow for the reason that arsenic having a small diffusion coefficient can be used as an impurity for threshold control, and the resistor used in a voltage dividing circuit or CR circuit is formed of polycrystalline silicon thinner than the polycrystalline silicon of the same layer as the gate electrode or a thin film metal.

Abstract: In a power management semiconductor device or analog semiconductor device having a CMOS and a resistor, a conductivity type of a gate electrode of the CMOS is P-type as to both an NMOS and a PMOS, a short channel and a low threshold voltage are possible since an E-type PMOS is surface channel type, the short channel and the low threshold voltage are possible since a buried channel type NMOS is extremely shallow for the reason that arsenic having a small diffusion coefficient can be used as an impurity for threshold control, and the resistor used in a voltage dividing circuit or CR circuit is formed of polycrystalline silicon thinner than the polycrystalline silicon of the same layer as the gate electrode or a thin film metal.

Abstract: To provide a method of manufacturing a semiconductor device in which an epitaxial growth film is formed on a semiconductor substrate having a buried layer, which is capable of reducing the manufacturing time of the semiconductor device or reducing the IC chip area. The method of manufacturing a semiconductor device is characterized by including a process of selecting the concentration of the p-type conductive impurities which put the surface of the silicon semiconductor substrate into a full amorphous state and conducting doping with the impurities.

Abstract: A MOS semiconductor device comprises a semiconductor substrate having source and drain regions, a first insulating film disposed over the substrate in a space overlapping opposed edges of the source and drain regions, and a gate electrode disposed on the first insulating film. A second insulating film is disposed at overlapping portions between the gate electrode and the source and drain regions to prevent the formation of a space therebetween.