Patents by Inventor Sumio Ogawa

Sumio Ogawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11294306
    Abstract: A recording medium of an embodiment includes a base material; a first color development layer that is located on the base material and absorbs light of a given wavelength to develop color; a second color development layer that is located closer to an incident side of the light than the first color development layer, transmits visible light and the light, and develops a color by heat; and a photothermal conversion layer that is located closer to an incident side of the light than the second color development layer intended to develop a color, transmits the visible light, and absorbs the light to photo-thermally convert the light into the heat.
    Type: Grant
    Filed: October 9, 2019
    Date of Patent: April 5, 2022
    Assignee: Toshiba Infrastructure Systems & Solutions Corporation
    Inventors: Nobuki Nemoto, Sumio Ogawa, Yasuo Fujimori, Yuuji Yoshida
  • Publication number: 20200117122
    Abstract: A recording medium of an embodiment includes a base material; a first color development layer that is located on the base material and absorbs light of a given wavelength to develop color; a second color development layer that is located closer to an incident side of the light than the first color development layer, transmits visible light and the light, and develops a color by heat; and a photothermal conversion layer that is located closer to an incident side of the light than the second color development layer intended to develop a color, transmits the visible light, and absorbs the light to photo-thermally convert the light into the heat.
    Type: Application
    Filed: October 9, 2019
    Publication date: April 16, 2020
    Inventors: Nobuki Nemoto, Sumio Ogawa, Koshin Fujimori, Yuji Yoshida
  • Patent number: 10366855
    Abstract: Some embodiments include a fuse element assembly having a first portion configured to rupture as materials of the first portion flow to a second portion through electromigration. The assembly has a second portion configured to accumulate the materials that have flowed from the first portion. The assembly also has a control element configured to divide the flow of materials into at least two paths along the second portion. The first portion may be a fuse-link and the second portion may be a cathode coupled to the fuse-link through a narrow neck region. The control element may be, for example, a slit, a hole, a conductive contact, etc.
    Type: Grant
    Filed: August 24, 2017
    Date of Patent: July 30, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Sumio Ogawa
  • Publication number: 20170372861
    Abstract: Some embodiments include a fuse element assembly having a first portion configured to rupture as materials of the first portion flow to a second portion through electromigration. The assembly has a second portion configured to accumulate the materials that have flowed from the first portion. The assembly also has a control element configured to divide the flow of materials into at least two paths along the second portion. The first portion may be a fuse-link and the second portion may be a cathode coupled to the fuse-link through a narrow neck region. The control element may be, for example, a slit, a hole, a conductive contact, etc.
    Type: Application
    Filed: August 24, 2017
    Publication date: December 28, 2017
    Inventor: Sumio Ogawa
  • Patent number: 9773632
    Abstract: Some embodiments include a fuse element assembly having a first portion configured to rupture as materials of the first portion flow to a second portion through electromigration. The assembly has a second portion configured to accumulate the materials that have flowed from the first portion. The assembly also has a control element configured to divide the flow of materials into at least two paths along the second portion. The first portion may be a fuse-link and the second portion may be a cathode coupled to the fuse-link through a narrow neck region. The control element may be, for example, a slit, a hole, a conductive contact, etc.
    Type: Grant
    Filed: September 8, 2015
    Date of Patent: September 26, 2017
    Assignee: Micron Technology, Inc.
    Inventor: Sumio Ogawa
  • Publication number: 20170069454
    Abstract: Some embodiments include a fuse element assembly having a first portion configured to rupture as materials of the first portion flow to a second portion through electromigration. The assembly has a second portion configured to accumulate the materials that have flowed from the first portion. The assembly also has a control element configured to divide the flow of materials into at least two paths along the second portion. The first portion may be a fuse-link and the second portion may be a cathode coupled to the fuse-link through a narrow neck region. The control element may be, for example, a slit, a hole, a conductive contact, etc.
    Type: Application
    Filed: September 8, 2015
    Publication date: March 9, 2017
    Inventor: Sumio Ogawa
  • Publication number: 20120199943
    Abstract: An element isolation region exists at a side opposite to a diffusion layer region as seen from a channel region, without another electrode to which the same potential as one applied to the diffusion layer region is applied interposed between the channel region and the element isolation region. The electric field applied to the gate insulating film is not uniform and the magnitude of the electric field is increased when approaching closer to the diffusion layer region. Therefore, breakdown is likely to occur at parts closer to the diffusion layer region.
    Type: Application
    Filed: April 16, 2012
    Publication date: August 9, 2012
    Applicant: ELPIDA MEMORY, INC.
    Inventor: Sumio OGAWA
  • Patent number: 8179709
    Abstract: An element isolation region exists at a side opposite to a diffusion layer region as seen from a channel region, without another electrode to which the same potential as one applied to the diffusion layer region is applied interposed between the channel region and the element isolation region. The electric field applied to the gate insulating film is not uniform and the magnitude of the electric field is increased when approaching closer to the diffusion layer region. Therefore, breakdown is likely to occur at parts closer to the diffusion layer region.
    Type: Grant
    Filed: August 22, 2008
    Date of Patent: May 15, 2012
    Assignee: Elpida Memory, Inc.
    Inventor: Sumio Ogawa
  • Patent number: 7952950
    Abstract: An anti-fuse circuit according to the present invention includes an anti-fuse element that holds data in a nonvolatile manner and a latch circuit that temporarily holds data to be written to the anti-fuse element. The writing to the latch circuit can be performed in the order of nanoseconds, and thus, even when the defective addresses respectively different are written in a plurality of chips, a writing process to the latch circuit can be completed in a very short period of time. Thereby, an actual process for writing to the anti-fuse element can be performed in parallel for the chips, and as a result, the process for writing to the anti-fuse element can be performed at high speed.
    Type: Grant
    Filed: October 22, 2008
    Date of Patent: May 31, 2011
    Assignee: Elpida Memory, Inc.
    Inventors: Shinichi Miyatake, Sumio Ogawa
  • Patent number: 7868417
    Abstract: A semiconductor device includes plural fuse elements which can be disconnected by irradiating a laser beam, and attenuation members which are located between the plural fuse elements as viewed two-dimensionally and can attenuate the laser beam. Each attenuation member includes plural columnar bodies. With this arrangement, the attenuation members including plural columnar units absorb the laser beam leaked out from a fuse element to be disconnected to a semiconductor substrate side. The laser beam is also scattered by Fresnel diffraction. Therefore, the columnar body can efficiently attenuate the laser beam, without generating a crack in the insulation film by absorbing excessive energy.
    Type: Grant
    Filed: January 25, 2008
    Date of Patent: January 11, 2011
    Assignee: Elpida Memory, Inc.
    Inventor: Sumio Ogawa
  • Patent number: 7755163
    Abstract: To provide an antifuse element comprising a gate electrode, a depletion channel region, a gate insulating film between the gate electrode and the channel region, and a diffusion layer region forming a junction with the channel region. An end of the gate electrode coincides substantially with a boundary between the channel region and the diffusion layer region as seen from a planar view, and is formed in a zigzag configuration. The end of the gate electrode is longer than the end with linear configuration and the end of the gate insulating film is likely to be subjected to breakdown.
    Type: Grant
    Filed: July 24, 2008
    Date of Patent: July 13, 2010
    Assignee: Elpida Memory, Inc.
    Inventor: Sumio Ogawa
  • Patent number: 7613056
    Abstract: In a semiconductor memory device provided with a redundancy circuit for conducting a repair of defective memory cells, the memory cell defects which are unevenly distributed can be efficiently repaired. The semiconductor memory device has a plurality of memory blocks, and the memory block includes a plurality of segments. A redundancy memory block which substitutes for defective data of a segment is physically provided to each of the plurality of memory blocks. A block address of the redundancy memory block is logically allocated to the plurality of memory blocks in common.
    Type: Grant
    Filed: July 10, 2008
    Date of Patent: November 3, 2009
    Assignee: Elpida Memory, Inc.
    Inventors: Sumio Ogawa, Yasuji Koshikawa
  • Patent number: 7550788
    Abstract: A semiconductor device includes a lower electrode, an upper electrode, and a fuse element that connects the lower electrode and the upper electrode. The height of the fuse element is greater than the depth of focus of a laser beam to be irradiated. The diameter of the fuse element is smaller than the diffraction limit of the laser beam. Thus, in the present invention, a vertically long fuse element is used, so that it is possible to efficiently absorb the energy of the laser beam. It is possible to cut the fuse element by using an optical system having a small depth of focus, so that the damage imposed on a member located above or below the fuse element is very small. As a result, the fuse element can be without destructing the passivation film.
    Type: Grant
    Filed: January 9, 2007
    Date of Patent: June 23, 2009
    Assignee: Elpida Memory, Inc.
    Inventor: Sumio Ogawa
  • Publication number: 20090109790
    Abstract: An anti-fuse circuit according to the present invention includes an anti-fuse element that holds data in a nonvolatile manner and a latch circuit that temporarily holds data to be written to the anti-fuse element. The writing to the latch circuit can be performed in the order of nanoseconds, and thus, even when the defective addresses respectively different are written in a plurality of chips, a writing process to the latch circuit can be completed in a very short period of time. Thereby, an actual process for writing to the anti-fuse element can be performed in parallel for the chips, and as a result, the process for writing to the anti-fuse element can be performed at high speed.
    Type: Application
    Filed: October 22, 2008
    Publication date: April 30, 2009
    Applicant: Elpida Memory, Inc.
    Inventors: Shinichi Miyatake, Sumio Ogawa
  • Publication number: 20090052221
    Abstract: An element isolation region exists at a side opposite to a diffusion layer region as seen from a channel region, without another electrode to which the same potential as one applied to the diffusion layer region is applied interposed between the channel region and the element isolation region. The electric field applied to the gate insulating film is not uniform and the magnitude of the electric field is increased when approaching closer to the diffusion layer region. Therefore, breakdown is likely to occur at parts closer to the diffusion layer region.
    Type: Application
    Filed: August 22, 2008
    Publication date: February 26, 2009
    Applicant: ELPIDA MEMORY, INC.
    Inventor: Sumio OGAWA
  • Publication number: 20090026577
    Abstract: To provide an antifuse element comprising a gate electrode, a depletion channel region, a gate insulating film between the gate electrode and the channel region, and a diffusion layer region forming a junction with the channel region. An end of the gate electrode coincides substantially with a boundary between the channel region and the diffusion layer region as seen from a planar view, and is formed in a zigzag configuration. The end of the gate electrode is longer than the end with linear configuration and the end of the gate insulating film is likely to be subjected to breakdown.
    Type: Application
    Filed: July 24, 2008
    Publication date: January 29, 2009
    Applicant: ELPIDA MEMORY, INC.
    Inventor: Sumio Ogawa
  • Publication number: 20080279020
    Abstract: In a semiconductor memory device provided with a redundancy circuit for conducting a repair of defective memory cells, the memory cell defects which are unevenly distributed can be efficiently repaired. The semiconductor memory device has a plurality of memory blocks, and the memory block includes a plurality of segments. A redundancy memory block which substitutes for defective data of a segment is physically provided to each of the plurality of memory blocks. A block address of the redundancy memory block is logically allocated to the plurality of memory blocks in common.
    Type: Application
    Filed: July 10, 2008
    Publication date: November 13, 2008
    Applicant: ELPIDA MEMORY, INC.
    Inventors: Sumio OGAWA, Yasuji KOSHIKAWA
  • Patent number: 7417908
    Abstract: In a semiconductor memory device provided with a redundancy circuit for conducting a repair of defective memory cells, the memory cell defects which are unevenly distributed can be efficiently repaired. The semiconductor memory device has a plurality of memory blocks, and the memory block includes a plurality of segments. A redundancy memory block which substitutes for defective data of a segment is physically provided to each of the plurality of memory blocks. A block address of the redundancy memory block is logically allocated to the plurality of memory blocks in common.
    Type: Grant
    Filed: July 13, 2004
    Date of Patent: August 26, 2008
    Assignee: Elpida Memory, Inc.
    Inventors: Sumio Ogawa, Yasuji Koshikawa
  • Publication number: 20080179708
    Abstract: A semiconductor device includes plural fuse elements which can be disconnected by irradiating a laser beam, and attenuation members which are located between the plural fuse elements as viewed two-dimensionally and can attenuate the laser beam. Each attenuation member includes plural columnar bodies. With this arrangement, the attenuation members including plural columnar units absorb the laser beam leaked out from a fuse element to be disconnected to a semiconductor substrate side. The laser beam is also scattered by Fresnel diffraction. Therefore, the columnar body can efficiently attenuate the laser beam, without generating a crack in the insulation film by absorbing excessive energy.
    Type: Application
    Filed: January 25, 2008
    Publication date: July 31, 2008
    Applicant: ELPIDA MEMORY, INC.
    Inventor: Sumio Ogawa
  • Publication number: 20080179707
    Abstract: A semiconductor device includes plural fuse elements that can be disconnected by irradiating a laser beam, lower-layer wirings that are located lower than the use elements, and plural through-hole electrodes for connecting between the fuse elements and the lower-layer wirings. The through-hole electrodes are provided at both ends of the fuse elements in the longitudinal direction, and a plurality of fuse elements are laid out on substantially a straight line in an A direction as a longitudinal direction. Accordingly, at the time of disconnecting a predetermined fuse element, through-hole electrodes connected to this fuse element become a shade, and unnecessary energy of a laser beam is not directly irradiated to other through-hole electrodes.
    Type: Application
    Filed: January 24, 2008
    Publication date: July 31, 2008
    Applicant: Elpida Memory, Inc.
    Inventor: Sumio Ogawa