Abstract: A computer program-implemented logic circuit simulation receives data describing the configuration of a logic circuit to be simulated, and a library of component characteristics incorporated in the circuit. Signals are classified as a first type always to be "watched" or as a second type to be evaluated only upon transition of a watched signal to an activated logic state. The circuit is partitioned into evaluation blocks, each one containing components and input lines thereto carrying only signals to be evaluated. The content of the block is simulated by "lump simulation", i.e., Boolean calculation, in response to a change to the activated logic state in the watched signal for the block. The maximum delay associated with the block is compared to the difference between the present time and the time of change of the watched signal to the activated state.