Patents by Inventor Sumio Yamamoto

Sumio Yamamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5221893
    Abstract: In a method of diagnosing deterioration of a paint film, a probe is applied to the surface of a paint film. A voltage having a predetermined waveform is applied by a preamplifier across the probe and a base metal on which the paint film is formed. A current flowing through the paint film is measured by the preamplifier. An analog signal indicative of a measured current value is converted to a corresponding digital signal by an analog-to-digital converter. A personal computer operates to analyze the digital signal in accordance with a predetermined analyzing procedure so that the degree of deterioration of the paint film is determined. The resultant determination is displayed on the display.
    Type: Grant
    Filed: February 20, 1992
    Date of Patent: June 22, 1993
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takeshi Kondou, Sumio Yamamoto
  • Patent number: 4999402
    Abstract: A methacrylic acid ester composition comprising 10 to 50 parts by weight of a cross-linked acrylic acid ester elastomer (A) and 50 to 90 parts by weight of a resin component, the total amount of the elastomer (A) and the resin component being 100 parts by weight; which is prepared by(a) preparing the cross-linked acrylic acid ester elastomer (A) by emulsion-polymerization,(b) adding a monomer component (B) to the elastomer (A) in the emulsion, and(c) polymerizing a monomer mixture (2) in the presence of the elastomer (A) to give the resin component.The composition is excellent in the processibility and can provide the film having the excellent transparency, weatherability, flexbility and whitening resistance to hot water.
    Type: Grant
    Filed: September 6, 1988
    Date of Patent: March 12, 1991
    Assignee: Kanegafuchi Kagaku Kogyo Kabushiki Kaisha
    Inventors: Sumio Yamamoto, Shinichi Sakurai
  • Patent number: 4849368
    Abstract: Disclosed is a method of producing a compound semiconductor device comprising an enhancement-mode transistor and a depletion-mode transistor, each of which has a heterojunction and utilizes a two-dimensional electron gas. The method of producing the device comprises the steps of: forming an undoped GaAs channel layer on a semi-insulating GaAs substrate; forming an N-type AlGaAs electron-supply layer so as to form the heterojunction; forming an N-type GaAs layer; forming an AlGaAs layer; selectively etching the AlGaAs layer to form a recess; performing an etching treatment using an etchant which can etch rapidly GaAs and etch slowly AlGaAs to form simultaneously grooves for gate electrodes of the enhancement-mode transistor and the depletion-mode transistor, the bottoms of the grooves being in the N-type AlGaAs layer and the distance between the bottoms being equal to the thickness of the AlGaAs layer; and forming simultaneously the gate electrodes in the grooves.
    Type: Grant
    Filed: January 21, 1988
    Date of Patent: July 18, 1989
    Assignee: Fujitsu Limited
    Inventors: Yoshimi Yamashita, Kinjiro Kosemura, Hidetoshi Ishiwari, Sumio Yamamoto, Shigeru Kuroda
  • Patent number: 4742379
    Abstract: A compound semiconductor device comprises an enhancement-mode transistor and a depletion-mode transistor, each of which has a heterojunction and utilizes a two-dimensional electron gas. The method of producing the device comprises the steps of: forming an undoped GaAs channel layer on a semi-insulating GaAs substrate; forming an N-type AlGaAs electron-supply layer so as to form the heterojunction; forming an N-type GaAs layer; forming an AlGaAs layer; selectively etching the AlGaAs layer to form a recess; performing an etching treatment using an etchant which can etch rapidly GaAs and etch slowly AlGaAs to form simultaneously grooves for gate electrodes of the enhancement-mode transistor and the depletion-mode transistor, the bottoms of the grooves being in the N-type AlGaAs layer and the distance between the bottoms being equal to the thickness of the AlGaAs layer; and forming simultaneously the gate electrodes in the grooves.
    Type: Grant
    Filed: November 29, 1984
    Date of Patent: May 3, 1988
    Assignee: Fujitsu Limited
    Inventors: Yoshimi Yamashita, Kinjiro Kosemura, Hidetoshi Ishiwari, Sumio Yamamoto, Shigeru Kuroda
  • Patent number: 4663572
    Abstract: By application of a predetermined period of relatively higher magnitude of electron beam emission from the cathode of the electron gun to the anode maintained at high voltage the potential gradient on the inside of the neck portion of a cathode ray tube is stabilized and the phenomenon of electron beam drift is thus suppressed effectively.
    Type: Grant
    Filed: October 20, 1983
    Date of Patent: May 5, 1987
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Sumio Yamamoto
  • Patent number: 4590232
    Abstract: A postchlorinated polyvinyl chloride composition having high processability for preparing molded products of outstanding properties comprises postchlorinated polyvinyl chloride and a copolymer of methyl methacrylate and a styrene monomer blended with the chloride. The composition has good thermal fluidity with good releasability from metal surface in processing and gives molded products of a high softening point and outstanding transparency.
    Type: Grant
    Filed: March 11, 1985
    Date of Patent: May 20, 1986
    Assignee: Kanegafuchi Kagaku Kogyo Kabushiki Kaisha
    Inventors: Yoshihisa Tsubokura, Sumio Yamamoto, Eiji Aoishi, Tamio Fujita
  • Patent number: 4578343
    Abstract: A method for producing a field effect type semiconductor device includes the steps of forming a semiconductor active layer on a substrate, forming a resist layer on the semiconductor active layer, exposing a first portion of the resist layer in accordance with a gate electrode pattern, carrying out auxiliary exposure of a second portion near the first portion after or before the exposure of the first portion. The method further includes developing the exposed resist layer, forming a recess in the semiconductor active layer by etching the exposed semiconductor active layer using the resist layer as a mask and forming a gate electrode on the surface of the recess using the resist layer as a mask. This method improves the series resistance between the source electrode and the gate electrode, and also improves the Schottky withstand voltage between the drain electrode and the gate electrode.
    Type: Grant
    Filed: March 28, 1985
    Date of Patent: March 25, 1986
    Assignee: Fujitsu Limited
    Inventors: Kinjiro Kosemura, Yoshimi Yamashita, Noriaki Nakayama, Sumio Yamamoto
  • Patent number: 4546467
    Abstract: A monitoring device for monitoring the status of communication units connected to a common transmission medium. The monitoring device sequentially addresses each communication unit and transmits to the addressed unit an inquiry frame which includes in addition to the destination address, a source address field and a control information field. The addressed communication unit, if operating responds with a reply frame including the destination address of the monitor, its address, and a status information field. The received status information is compared with a previously received status information from the addressed control unit, and a primary fault is indicated when the compared informations do not coincide. A secondary fault is indicated if no reply frame is received from an addressed communication unit within a predetermined time from the transmission of the inquiry frame.
    Type: Grant
    Filed: February 3, 1983
    Date of Patent: October 8, 1985
    Assignee: Nippon Electric Co., Ltd.
    Inventor: Sumio Yamamoto
  • Patent number: 4443704
    Abstract: A method of electron beam exposure in which a plurality of sets of reference values for setting the conditions for electron beam exposure are found in relation to a plurality of sizing marks which are successively arrayed at positions in the vicinity of the pattern area of a specimen, and the exposure condition values corresponding to registration marks on the surface of the specimen are derived from these said reference values for setting the exposure conditions.
    Type: Grant
    Filed: June 11, 1982
    Date of Patent: April 17, 1984
    Assignee: Fujitsu Limited
    Inventors: Yoshimi Yamashita, Sumio Yamamoto