Abstract: An integrated circuit (IC) provides an improved fail-safe signal to a circuit sharing a fail-safe pin at which the voltage can be greater than the voltage of an upper rail. The IC includes a first circuit segment that receives a first fail-safe signal and a first power-down signal and provides an intermediate signal, wherein the first fail-safe signal indicates when the voltage at the fail-safe pin is greater than the upper rail and the first power-down signal indicates when the module is powered down, and a second circuit segment connected to receive the intermediate signal and to provide the improved fail-safe signal to the module.

Abstract: A circuit includes a filter, a comparator, and converter. A first input of the comparator couples to the output of the filter. A second input of the comparator is configured to receive ramp signal. An input of the converter couples to the output of the comparator. The circuit also includes a dual minimum pulse generator having an input coupled to the output of the converter. The dual minimum pulse generator is configured to, responsive to an input pulse on the input of the dual minimum pulse generator having a pulse width less than a predetermined delay time period, generate a pulse on the first output of the dual minimum pulse generator that has a pulse width equal to a sum of the pulse width of the input pulse and the predetermined delay time period. A driver is coupled to the output of the dual minimum pulse generator.

Abstract: A circuit includes a filter, a comparator, and converter. A first input of the comparator couples to the output of the filter. A second input of the comparator is configured to receive ramp signal. An input of the converter couples to the output of the comparator. The circuit also includes a dual minimum pulse generator having an input coupled to the output of the converter. The dual minimum pulse generator is configured to, responsive to an input pulse on the input of the dual minimum pulse generator having a pulse width less than a predetermined delay time period, generate a pulse on the first output of the dual minimum pulse generator that has a pulse width equal to a sum of the pulse width of the input pulse and the predetermined delay time period. A driver is coupled to the output of the dual minimum pulse generator.

Abstract: At least some embodiments are directed to a system comprising a capacitor coupled to a voltage supply rail and configured to carry a capacitor current that comprises first and second parts. The capacitor current is an alternating current (AC). A first current mirror component may couple to the capacitor and to the voltage supply rail and is configured to carry the first part of the capacitor current. A second current mirror component couples to the voltage supply rail and is configured to carry the second part of the capacitor current. The second part of the capacitor current is proportionally related to the first part of the capacitor current. A circuit couples to the second current mirror component. The capacitor and the first and second current mirror components are configured to attenuate a common mode noise current flowing to the circuit.

Abstract: A circuit includes a filter, a comparator, and converter. A first input of the comparator couples to the output of the filter. A second input of the comparator is configured to receive ramp signal. An input of the converter couples to the output of the comparator. The circuit also includes a dual minimum pulse generator having an input coupled to the output of the converter. The dual minimum pulse generator is configured to, responsive to an input pulse on the input of the dual minimum pulse generator having a pulse width less than a predetermined delay time period, generate a pulse on the first output of the dual minimum pulse generator that has a pulse width equal to a sum of the pulse width of the input pulse and the predetermined delay time period. A driver is coupled to the output of the dual minimum pulse generator.

Abstract: At least some embodiments are directed to a system comprising a capacitor coupled to a voltage supply rail and configured to carry a capacitor current that comprises first and second parts. The capacitor current is an alternating current (AC). A first current mirror component may couple to the capacitor and to the voltage supply rail and is configured to carry the first part of the capacitor current. A second current mirror component couples to the voltage supply rail and is configured to carry the second part of the capacitor current. The second part of the capacitor current is proportionally related to the first part of the capacitor current. A circuit couples to the second current mirror component. The capacitor and the first and second current mirror components are configured to attenuate a common mode noise current flowing to the circuit.

Abstract: At least some embodiments are directed to a system comprising a capacitor coupled to a voltage supply rail and configured to carry a capacitor current that comprises first and second parts. The capacitor current is an alternating current (AC). A first current mirror component may couple to the capacitor and to the voltage supply rail and is configured to carry the first part of the capacitor current. A second current mirror component couples to the voltage supply rail and is configured to carry the second part of the capacitor current. The second part of the capacitor current is proportionally related to the first part of the capacitor current. A circuit couples to the second current mirror component. The capacitor and the first and second current mirror components are configured to attenuate a common mode noise current flowing to the circuit.

Abstract: An integrated circuit (IC) provides an improved fail-safe signal to a circuit sharing a fail-safe pin at which the voltage can be greater than the voltage of an upper rail. The IC includes a first circuit segment that receives a first fail-safe signal and a first power-down signal and provides an intermediate signal, wherein the first fail-safe signal indicates when the voltage at the fail-safe pin is greater than the upper rail and the first power-down signal indicates when the module is powered down, and a second circuit segment connected to receive the intermediate signal and to provide the improved fail-safe signal to the module.

Abstract: An integrated circuit (IC) provides an improved fail-safe signal to a circuit sharing a fail-safe pin at which the voltage can be greater than the voltage of an upper rail. The IC includes a first circuit segment that receives a first fail-safe signal and a first power-down signal and provides an intermediate signal, wherein the first fail-safe signal indicates when the voltage at the fail-safe pin is greater than the upper rail and the first power-down signal indicates when the module is powered down, and a second circuit segment connected to receive the intermediate signal and to provide the improved fail-safe signal to the module.

Abstract: At least some embodiments are directed to a system comprising a capacitor coupled to a voltage supply rail and configured to carry a capacitor current that comprises first and second parts. The capacitor current is an alternating current (AC). A first current mirror component may couple to the capacitor and to the voltage supply rail and is configured to carry the first part of the capacitor current. A second current mirror component couples to the voltage supply rail and is configured to carry the second part of the capacitor current. The second part of the capacitor current is proportionally related to the first part of the capacitor current. A circuit couples to the second current mirror component. The capacitor and the first and second current mirror components are configured to attenuate a common mode noise current flowing to the circuit.

Abstract: Disclosed examples include switched capacitor integrator circuits including an amplifier, a feedback capacitor, a sampling capacitor, a loading capacitor and a switching circuit, along with a controller that operates the switching circuit to sample an input signal to the sampling capacitor during a sample portion of a given sample and hold cycle, to couple the sampling capacitor to an amplifier input during a first hold portion of each sample and hold cycle, and to couple the sampling capacitor and the loading capacitor to the amplifier input in a second hold portion of each sample and hold cycle to reduce the bandwidth and power consumption by the integrator circuit.

Abstract: An integrated circuit (IC) provides an improved fail-safe signal to a circuit sharing a fail-safe pin at which the voltage can be greater than the voltage of an upper rail. The IC includes a first circuit segment that receives a first fail-safe signal and a first power-down signal and provides an intermediate signal, wherein the first fail-safe signal indicates when the voltage at the fail-safe pin is greater than the upper rail and the first power-down signal indicates when the module is powered down, and a second circuit segment connected to receive the intermediate signal and to provide the improved fail-safe signal to the module.