Patents by Inventor Sumit Kumar Jha

Sumit Kumar Jha has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210090251
    Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for training a machine learning model to segment magnified images of tissue samples. The method includes obtaining a magnified image of a tissue sample; processing an input comprising: the image, features derived from the image, or both, in accordance with current values of model parameters of a machine learning model to generate an automatic segmentation of the image into a plurality of tissue classes; providing, to a user through a user interface, an indication of: (i) the image, and (ii) the automatic segmentation of the image; determining an edited segmentation of the image, comprising applying modifications specified by the user to the automatic segmentation of the image; and determining updated values of the model parameters of the machine learning model based the edited segmentation of the image.
    Type: Application
    Filed: September 22, 2020
    Publication date: March 25, 2021
    Inventors: Sumit Kumar Jha, Aditya Sista, Ganesh Kumar Mohanur Raghunathan, Ubhay Kumar, Kedar Sapre
  • Publication number: 20200234441
    Abstract: An imaging system includes a microscope to generate magnified images of regions of interest of a tissue sample, a camera to capture and store the magnified images, and a controller. The controller is configured to, for each magnification level in a sequence of increasing magnification levels, image one or more regions of interest of the tissue sample at the current magnification level. For each region of interest, data is generated defining one or more refined regions of interest based on the magnified image of the region of interest of the tissue sample at the current magnification level. Each refined region of interest corresponds to a proper subset of the tissue sample, and the refined regions of interest of the tissue sample provide the regions of interest to be imaged at a next magnification level from the sequence of increasing magnification levels.
    Type: Application
    Filed: January 17, 2020
    Publication date: July 23, 2020
    Inventors: Parijat P. Prabhudesai, Ganesh Kumar Mohanur Raghunathan, Aditya Sista, Sumit Kumar Jha, Narasimha Murthy Chandan
  • Publication number: 20200074146
    Abstract: Certain aspects of the present disclosure provide techniques for automatically detecting and classifying tumor regions in a tissue slide. The method generally includes obtaining a digitized tissue slide from a tissue slide database and determining, based on output from a tissue classification module, a type of tissue of shown in the digitized tissue slide. The method further includes determining, based on output from a tumor classification model for the type of tissue, a region of interest (ROI) of the digitized tissue slide and generating a classified slide showing the ROI of the digitized tissue slide and an estimated diameter of the ROI. The method further includes displaying on an image display unit, the classified slide and user interface (UI) elements enabling a pathologist to enter input related to the classified slide.
    Type: Application
    Filed: August 28, 2019
    Publication date: March 5, 2020
    Inventors: Parijat Prakash PRABHUDESAI, Ganesh Kumar MOHANUR RAGHUNATHAN, Sumit Kumar JHA, Aditya SISTA, Narasimha Murthy CHANDAN
  • Publication number: 20190051825
    Abstract: An in-memory computing architecture is disclosed that can evaluate the transitive closure of graphs using the natural parallel flow of information in 3-D nanoscale crossbars. The architecture can be implemented using 3-D crossbar architectures with as few as two layers of 1-diode 1-resistor (1D1R) interconnects. The architecture avoids memory-processor bottlenecks and can hence scale to large graphs. The approach leads to a runtime complexity of O(n2) using O(n2) memristor devices. This compares favorably to conventional algorithms with a time complexity of O((n3)/p+(n2) log p) on p processors. The approach takes advantage of the dynamics of 3-D crossbars not available on 2-D crossbars.
    Type: Application
    Filed: July 30, 2018
    Publication date: February 14, 2019
    Inventors: Alvaro Vasquez, Sumit Kumar Jha
  • Patent number: 9552453
    Abstract: In the physical design of an integrated circuit, comparing metal fill locations with an average least resistance path (LRP) for a cell and then filling the location with either power or ground tiles based on the comparison. For each metal layer, all of the metal fill locations are determined and nearby metal fills, i.e., those within a predetermined radius of a located metal fill are connected. A Design Rule Check (DRC) is performed to ensure that connected metal fills meet design specifications, for example, that connected metal fills are not too close to a signal line. The metal fill method improves the power integrity of the design.
    Type: Grant
    Filed: September 22, 2015
    Date of Patent: January 24, 2017
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Rishabh Agarwal, Sumit Kumar Jha
  • Patent number: 9319047
    Abstract: Memristor-based nano-crossbar computing is a revolutionary computing paradigm that does away with the traditional Von Neumann architectural separation of memory and computation units. The computation of Boolean formulas using memristor circuits has been a subject of several recent investigations. Crossbar computing, in general, has also been a topic of active interest, but sneak paths have posed a hurdle in the design of pervasive general-purpose crossbar computing paradigms. Various embodiments are disclosed which demonstrate that sneak paths in nano-crossbar computing can be exploited to design a Boolean-formula evaluation strategy. Such nano-crossbar designs are also an effective approach for synthesizing high performance customized arithmetic and logic circuits.
    Type: Grant
    Filed: December 17, 2014
    Date of Patent: April 19, 2016
    Assignee: UNIVERSITY OF CENTRAL FLORIDA RESEARCH FOUNDATION, INC.
    Inventors: Sumit Kumar Jha, Dilia E. Rodriguez, Joseph E. Van Nostrand, Alvaro Velasquez