Abstract: Systems and methods for interleaving video sub-blocks in video coding are described herein. In one aspect, an apparatus includes a memory and a video coder. The memory stores a first video block and a second video block. The first video block and the second video block include sub-blocks. The video coder processes a first sub-block of the first video block according to a first process and a second process, and processes a second sub-block of the first video block according to the first process and the second process after processing the first sub-block of the first video block according to the first process and the second process. Further, the video coder processes a first sub-block of the second video block according to the first process before processing the second sub-block of the first video block according to the first process.

Abstract: Systems and methods for intra prediction video coding are described herein. In one aspect, an apparatus includes a processor and a memory. The processor divides a video block into a plurality of video sub-blocks having a first size. The video block includes video units and has an intra prediction mode, and each video sub-block of the plurality of video sub-blocks includes at least a non-zero integer number of video units of the video block. The processor further determines prediction variables for a first video sub-block of the plurality of video sub-blocks based on the intra prediction mode of the video block and determines a predicted video unit for each video unit of the first video sub-block based on the intra prediction mode of the video block and the prediction variables for the first video sub-block. The memory stores the predicted video units.

Abstract: Methods and systems for efficient searching of candidate blocks for inter-coding and/or intra coding are provided. In one innovative aspect, an apparatus for performing motion estimation is provided. The apparatus includes a processor configured to identify a number of candidate blocks of a frame of video data to be searched, at least one candidate block corresponding to a block of another frame of the video data. The processor is further configured to select one or more of the candidate blocks to search based on a distance between the candidate blocks. The processor is also configured to select a method for searching the selected candidate blocks based on a format of the video data. The processor is also configured to estimate the motion for the block of the another frame based on the selected method and the selected candidate blocks.

Abstract: Motion estimation in video compressions systems. A programmable motion estimator may be used to estimate a motion vector for a macroblock in a current frame by searching for a matching macroblock in a previous frame. A controller may be used to program the motion estimator to perform a particular search.

Abstract: This disclosure describes a scaler architecture for image and/or video processing. One aspect relates to an apparatus comprising an image processing unit, a memory, and a coder. The memory is configured to store processed image data from the image processing unit. The coder is configured to retrieve the stored, processed image data from the memory. The coder comprises a scaler configured to upscale the retrieved image data from the memory. The coder is configured to encode the scaled image data.

Abstract: Techniques for intensity compensation in video processing are provided. In one configuration, a wireless communication device compliant with the VC1-SMPTE standard (e.g., cellular phone, etc.) comprises a processor that is configured to execute instructions operative to reconstruct reference frames from a received video bitstream. A non-intensity-compensated copy of a reference frame of the bitstream is stored in a memory of the device and used for defining the displayable images and for on-the-fly generation of a stream of intensity-compensated pixels to perform motion compensation calculations for frames of the video bitstream.

Abstract: This disclosure describes a scaler architecture for image and/or video processing. One aspect relates to an apparatus comprising an image processing unit, a memory, and a coder. The memory is configured to store processed image data from the image processing unit. The coder is configured to retrieve the stored, processed image data from the memory. The coder comprises a scaler configured to upscale the retrieved image data from the memory. The coder is configured to encode the scaled image data.

Abstract: Motion estimation in video compressions systems. A programmable motion estimator may be used to estimate a motion vector for a macroblock in a current frame by searching for a matching macroblock in a previous frame. A controller may be used to program the motion estimator to perform a particular search.