Patents by Inventor Sumit Nagpal

Sumit Nagpal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250139123
    Abstract: A method includes receiving a request to reconcile a first set of data stored in a first datastore and a second set of data stored in a second datastore, retrieving, from the first datastore, the first set of data, and retrieving, from the second datastore, the second set of data. The first set of data includes one or more first rows each including a respective first data value and the second set of data includes one or more second rows each including a respective second data value. The method also includes determining a mismatch between a respective one of the first data values and a respective one of the second data values. Based on determining the mismatch, the method also includes updating the respective one of the second data values to match the respective one of the first data values.
    Type: Application
    Filed: January 3, 2025
    Publication date: May 1, 2025
    Applicant: Bristol-Myers Squibb Company
    Inventors: Sahith Doppalapudi, Sumit Nagpal
  • Patent number: 12282492
    Abstract: Provided herein are system, apparatus, device, method and/or computer program product embodiments, and/or combinations and sub-combinations thereof, for generating an output indicating differences in the data stored in disparate data storage devices and/or for reconciling data stored in disparate data storage devices. In an embodiment, a server loads a first subset of a first set of data corresponding to one or more first columns and a second subset of a second set of data corresponding to one or more second columns into a data repository. The server identifies one or more differences between the first subset of data and the second subset of data in the data repository, and causes display of the one or more differences. The server may generate an output including the first and second sets of data, and a visual indicator indicating each of the one or more differences and causes display of the output.
    Type: Grant
    Filed: June 24, 2022
    Date of Patent: April 22, 2025
    Assignee: Bristol-Myers Squibb Company
    Inventors: Sahith Doppalapudi, Sumit Nagpal
  • Publication number: 20250086007
    Abstract: Scheduling kernels on a system with heterogeneous compute circuits includes receiving, by a hardware processor, a plurality of kernels and a graph including a plurality of nodes corresponding to the plurality of kernels. The graph defines a control flow and a data flow for the plurality of kernels. The kernels are implemented within different ones of a plurality of compute circuits coupled to the hardware processor. A set of buffers for performing a job for the graph are allocated based, at least in part, on the data flow specified by the graph. Different ones of the kernels as implemented in the compute circuits are invoked based on the control flow defined by the graph.
    Type: Application
    Filed: September 11, 2023
    Publication date: March 13, 2025
    Applicant: Xilinx, Inc.
    Inventors: Sumit Nagpal, Abid Karumannil
  • Publication number: 20240211675
    Abstract: A design for a programmable integrated circuit (IC) is synthesized and includes an inference engine and a data transformer. A portion of the design including the data transformer is designated as a dynamic function exchange (DFX) module. The inference engine is excluded from the DFX module. The design is implemented, by placing and routing, such that the DFX module is confined to a defined physical area of the programmable integrated circuit. An abstract shell for the design specifying boundary connections of the DFX module as placed and routed is generated. A locked version of the design as placed and routed with the DFX module removed is generated. The method includes implementing a different data transformer as a further DFX module for the design using the abstract shell.
    Type: Application
    Filed: December 22, 2022
    Publication date: June 27, 2024
    Applicant: Xilinx, Inc.
    Inventors: Mohammed Bader Alam, Goutham Pocklassery, Ravishankar Menon, Sumit Nagpal, Mahesh Suresh Mahadurkar, Padmini Gopalakrishnan
  • Publication number: 20230153583
    Abstract: Processing of a neural network specification includes gathering first layers of a neural network graph into groups of layers based on profiled compute times of the layers and equalized compute times between the groups. Each group is a subgraph of one or more of the layers of the neural network. The neural network graph is compiled into instructions for pipelined execution of the neural network graph by compute circuits. The compiling includes designating, for each first subgraph of the subgraphs having output activations that are input activations of a second subgraph of the subgraphs, operations of the first subgraph to be performed by a first compute circuit and operations of the second subgraph to be performed by a second compute circuit. The compute circuits are configured to execute the instructions.
    Type: Application
    Filed: November 15, 2021
    Publication date: May 18, 2023
    Applicant: Xilinx, Inc.
    Inventors: Ashish Sirasao, Vishal Kumar Jain, Sumit Nagpal
  • Publication number: 20230048663
    Abstract: Provided herein are system, apparatus, device, method and/or computer program product embodiments, and/or combinations and sub-combinations thereof, for generating an output indicating differences in the data stored in disparate data storage devices and/or for reconciling data stored in disparate data storage devices. In an embodiment, a server loads a first subset of a first set of data corresponding to one or more first columns and a second subset of a second set of data corresponding to one or more second columns into a data repository. The server identifies one or more differences between the first subset of data and the second subset of data in the data repository, and causes display of the one or more differences. The server may generate an output including the first and second sets of data, and a visual indicator indicating each of the one or more differences and causes display of the output.
    Type: Application
    Filed: June 24, 2022
    Publication date: February 16, 2023
    Applicant: Bristol-Myers Squibb Company
    Inventors: Sahith DOPPALAPUDI, Sumit NAGPAL
  • Patent number: 11561826
    Abstract: Scheduling work of a machine learning application includes instantiating kernel objects by a computer processor in response to input of kernel definitions. Each kernel object is of a kernel type indicating a compute circuit. The computer processor generates a graph in a memory. Each node represents a task and specifies an assignment of the task to one or more of the kernel objects, and each edge represents a data dependency. Task queues are created in the memory and assigned to queue tasks represented by the nodes. Kernel objects are assigned to the task queues, and the tasks are enqueued by threads executing the kernel objects, based on assignments of the kernel objects to the task queues and assignments of the tasks to the kernel objects. Tasks are dequeued by the threads, and the compute circuits are activated to initiate processing of the dequeued tasks.
    Type: Grant
    Filed: November 12, 2020
    Date of Patent: January 24, 2023
    Assignee: XILINX, INC.
    Inventors: Sumit Nagpal, Abid Karumannil, Vishal Jain, Arun Kumar Patil
  • Patent number: 11003826
    Abstract: Strategies are stored in a memory arrangement, and each strategy includes a set of parameter settings for a design tool. The design tool identifies a set of features of an input circuit design and applies classification models to the input circuit design. Each classification model indicates one the strategies, and application of each classification model indicates a likelihood that use of the strategy would improve a metric of the input circuit design based on the set of features of the input circuit design. One strategy of the plurality of strategies is selected based on the likelihood that use of the one strategy would improve the metric of the input circuit design, and the design tool is configured with the set of parameter settings of the one strategy. The design tool then processes the input circuit design into implementation data that is suitable for making an integrated circuit (IC).
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: May 11, 2021
    Assignee: XILINX, INC.
    Inventors: Srinivasan Dasasathyan, Padmini Gopalakrishnan, Vishal Tripathy, Vikas N. Vedamurthy, Sumit Nagpal
  • Patent number: 10867093
    Abstract: Disclosed approaches for guiding actions in processing a circuit design include a design tool identifying first violations of design checks and determining severity levels of the first violations. The design tool determines for each violation, suggested actions associated with the violation and presents on a display, first data indicative of the suggested actions in order of the severity levels of the first violations. The first data include selectable objects, and each selectable object has an associated executable procedure. The design tool can execute the procedure associated with one of the selectable objects in response to selection and modify the circuit design in response to execution of the procedure.
    Type: Grant
    Filed: March 20, 2019
    Date of Patent: December 15, 2020
    Assignee: Xilinx, Inc.
    Inventors: John Blaine, Srinivasan Dasasathyan, Meghraj Kalase, Frederic Revenu, Veeresh Pratap Singh, Satish Bachina, Shail Bains, Padmini Gopalakrishnan, Sumit Nagpal, Gaurav Dutt Sharma
  • Patent number: 10067642
    Abstract: Core processing and parameterization may include detecting, using a processor, a super parameter within a core, and, responsive to the detecting, automatically creating, using the processor, a data structure within a memory element having a hierarchy and having a parameter of the core. The data structure may be set as a value of the super parameter of the core.
    Type: Grant
    Filed: March 5, 2015
    Date of Patent: September 4, 2018
    Assignee: XILINX, INC.
    Inventors: David Robinson, Sumit Nagpal, Prashanth Kumar, Shreegopal S. Agrawal
  • Patent number: 9710582
    Abstract: Implementing a circuit design may include, responsive to a user input selecting a design, executing an implementation script of the design using the processor. Executing the implementation script may generate instructions for generating a circuit design from the design. Responsive to the instructions and using the processor, cores of the design may be automatically instantiated and connected.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: July 18, 2017
    Assignee: XILINX, INC.
    Inventors: Sumit Nagpal, Siddharth Rele, Avdhesh Palliwal
  • Patent number: 9183337
    Abstract: A method of processing a circuit design in a circuit design tool includes: identifying selection of a parameterized core to be instantiated in a description of the circuit design managed by the circuit design tool and configured for implementation in target hardware; processing a configuration file for the parameterized core to select a set of parameter values from a plurality of sets of parameter values dynamically based at least in part on the target hardware; creating an instance of the parameterized core in the circuit design having the selected set of parameter values; and implementing the circuit design for the target hardware.
    Type: Grant
    Filed: August 8, 2014
    Date of Patent: November 10, 2015
    Assignee: XILINX, INC.
    Inventors: Sumit Nagpal, Sreevidya Maguluri, Prashanth Kumar
  • Patent number: 8938704
    Abstract: An exemplary method of implementing a circuit design for a programmable integrated circuit (IC) includes, on at least one programmed processor, performing operations including: generating a description of circuit components of the circuit design including first portion of a circuit module that is independent of assignment of resources of the programmable IC; assigning a plurality of the resources of the programmable IC to a plurality of the circuit components including determining at least one resource assignment for the circuit module; and generating a physical implementation of the circuit components for implementation in the programmable IC, including generating a second portion of the circuit module that is dependent on the at least one resource assignment, and combining the second portion of the circuit module with the first portion of the circuit module.
    Type: Grant
    Filed: July 28, 2014
    Date of Patent: January 20, 2015
    Assignee: Xilinx, Inc.
    Inventors: Siddharth Rele, David A. Knol, Sumit Nagpal, Avdhesh Palliwal, Brendan M. O'Higgins
  • Patent number: 8769477
    Abstract: A user interface for a computer-aided design tool includes a display. The display includes a visualization of a processor system of a system-on-a-chip (SOC). The visualization includes a plurality of blocks and each block represents a component of the processor system. Each block visually indicates a configuration status of the component represented by the block.
    Type: Grant
    Filed: January 31, 2013
    Date of Patent: July 1, 2014
    Assignee: Xilinx, Inc.
    Inventors: Yogesh Gathoo, Siddharth Rele, Gregory A. Brown, Avdhesh Palliwal, Gangadhar Budde, Sumit Nagpal