Patents by Inventor Sumit Varshney

Sumit Varshney has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11488904
    Abstract: A mechanism is provided to reduce noise effects on signals traversing bond wires of a SOC by forming a bond wire ring structure that decreases mutual inductance and capacitive coupling. Bond wires form the ring structure in a daisy chain connecting isolated ground leads at a semiconductor device package surrounding the semiconductor device. This structure reduces out-of-plane electromagnetic field interference generated by signals in lead wires, as well as mutual capacitance and mutual inductance.
    Type: Grant
    Filed: February 17, 2021
    Date of Patent: November 1, 2022
    Assignee: NXP B.V.
    Inventors: Ajay Kumar Sharma, Rishi Bhooshan, Sumit Varshney, Frank Martin Paglia
  • Publication number: 20220208672
    Abstract: A mechanism is provided to reduce noise effects on signals traversing bond wires of a SOC by forming a bond wire ring structure that decreases mutual inductance and capacitive coupling. Bond wires form the ring structure in a daisy chain connecting isolated ground leads at a semiconductor device package surrounding the semiconductor device. This structure reduces out-of-plane electromagnetic field interference generated by signals in lead wires, as well as mutual capacitance and mutual inductance.
    Type: Application
    Filed: February 17, 2021
    Publication date: June 30, 2022
    Applicant: NXP B.V.
    Inventors: Ajay Kumar Sharma, Rishi Bhooshan, Sumit Varshney, Frank Martin Paglia
  • Patent number: 9418873
    Abstract: A semiconductor device has an on-die decoupling capacitor that is shared between alternative high-speed interfaces. A capacitance pad is connected to the decoupling capacitor and internal connection pads are connected respectively to the alternative interfaces. Internal connection bond wires connect the decoupling capacitor to the selected interface through the capacitance pad and the internal connection pads in the same process as connecting the die to external electrical contacts of the device.
    Type: Grant
    Filed: August 24, 2014
    Date of Patent: August 16, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Shailesh Kumar, Vikas Garg, Sumit Varshney, Chetan Verma
  • Patent number: 9337140
    Abstract: A semiconductor device includes a semiconductor die having opposing first and second main surfaces, contact pads and a metal ring accessible from the first main surface, and signal leads surrounding and spaced from the die. Each of the signal leads has a first end near the die, a second end remote from the die, and a body extending between the first and second ends. A dummy lead frame is disposed between the signal leads first ends and the die, and connected to a fixed potential. First bond wires are coupled to respective ones of the signal leads and the contact pads. Second, shield bond wires, located adjacent to respective ones of the bond wires, are coupled to the dummy lead frame and the metal ring.
    Type: Grant
    Filed: September 1, 2015
    Date of Patent: May 10, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Shailesh Kumar, Rishi Bhooshan, Meng Kong Lye, Sumit Varshney, Chetan Verma
  • Publication number: 20160056099
    Abstract: A semiconductor device has an on-die decoupling capacitor that is shared between alternative high-speed interfaces. A capacitance pad is connected to the decoupling capacitor and internal connection pads are connected respectively to the alternative interfaces. Internal connection bond wires connect the decoupling capacitor to the selected interface through the capacitance pad and the internal connection pads in the same process as connecting the die to external electrical contacts of the device.
    Type: Application
    Filed: August 24, 2014
    Publication date: February 25, 2016
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Shailesh Kumar, Vikas Garg, Sumit Varshney, Chetan Verma
  • Patent number: 9271390
    Abstract: A semiconductor device has a multi-wire lead and a die having a multi-site bond pad. A shielding wire and a guarded wire both extend from the multi-wire lead to the multi-site bond pad. The shielding wire (or wires) provide active shielding to the guarded wire by simultaneously transmitting the same signal as the guarded wire between the multi-wire lead the multi-site bond pad.
    Type: Grant
    Filed: July 15, 2014
    Date of Patent: February 23, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Sunaina Srivastava, Raza Imam, Gagan Kansal, Sumit Varshney
  • Publication number: 20160021734
    Abstract: A semiconductor device has a multi-wire lead and a die having a multi-site bond pad. A shielding wire and a guarded wire both extend from the multi-wire lead to the multi-site bond pad. The shielding wire (or wires) provide active shielding to the guarded wire by simultaneously transmitting the same signal as the guarded wire between the multi-wire lead the multi-site bond pad.
    Type: Application
    Filed: July 15, 2014
    Publication date: January 21, 2016
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Sunaina Srivastava, Raza Imam, Gagan Kansal, Sumit Varshney
  • Patent number: 9147656
    Abstract: A shielding structure for use with semiconductor devices. The shielding structure has a base with fingers that are sized and shaped to extend within the space between pairs of adjacent leads. The base extends within the space between the die flag and the leads. The shielding structure is further connected to one of the grounded leads.
    Type: Grant
    Filed: July 11, 2014
    Date of Patent: September 29, 2015
    Assignee: FREESCALE SEMICONDUTOR, INC.
    Inventors: Sumit Varshney, Rishi Bhooshan, Meng Kong Lye, Chetan Verma