Patents by Inventor Sumitaka Gotou

Sumitaka Gotou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6359639
    Abstract: A thermal head driving integrated circuit capable of preventing the lowering of data transfer speed, and in which the number of bonding pads can be reduced as well as current consumption has a driver circuit in which at least two shift registers are series-arranged in front and rear stages to sequentially transfer print data in a serial signal manner to be read out in a batch mode to drive a plurality of heating resistive elements. A switch circuit is interposed between an output terminal of the front-staged shift register and an input terminal of the rear-staged shift register to selectively connect and disconnect the two shift registers.
    Type: Grant
    Filed: October 28, 1999
    Date of Patent: March 19, 2002
    Assignee: Seiko Instruments Inc.
    Inventors: Tatsuya Kitta, Yoshihide Kanakubo, Yasuhiro Moya, Kazutoshi Ishii, Sumitaka Gotou
  • Patent number: 6134136
    Abstract: Reducing the chip area while improving the manufacturing efficiency as well as reducing costs in a semiconductor integrated circuit device such as a thermal head driver IC. A plurality of terminal electrodes were provided within an external data input/output circuit with an input terminal and output terminal being electrically connected to each other. In addition, an input/output protection circuit was provided to a respective one of such plurality of terminal electrodes with the input terminal and output terminal electrically connected together.
    Type: Grant
    Filed: January 26, 1999
    Date of Patent: October 17, 2000
    Assignee: Seiko Instruments Inc.
    Inventors: Kazutoshi Ishii, Sumitaka Gotou, Yasuhiro Moya, Yoshihide Kanakubo, Tatuya Kitta
  • Patent number: 6107128
    Abstract: Since a field effect MOS transistor can be formed with a reduced number of manufacturing processes, a semiconductor integrated circuit device can be materialized at a low cost. A semiconductor device has a structure in which a gate electrode is provided in the vicinity of the surface of a semiconductor substrate through a gate insulating film, a second conductive type heavily doped impurity region is provided in a region adjacent to a part of the gate electrode through a part of the gate insulating film and a part of a thick oxide film, another second conductive type heavily doped impurity region is provided in a region adjacent to an opposite part of the gate electrode opposing the part of the gate electrode through the part of the gate insulating film and a part of another thick oxide film, and a first conductive type heavily doped impurity region for device isolation is provided so as to surround the gate electrode and the second conductive type heavily doped impurity regions.
    Type: Grant
    Filed: June 2, 1999
    Date of Patent: August 22, 2000
    Assignee: Seiko Instruments Inc.
    Inventors: Kazutoshi Ishii, Sumitaka Gotou, Yasuhiro Moya, Tatsuya Kitta, Yoshihide Kanakubo