Abstract: An adaptive equalization method updates the tap coefficient through utilization of the mean value of instantaneous gradient vectors, thereby ensuring the likelihood of pseudo transmission data that is generated from received data.

Abstract: It is an object of the present invention to simplify a multiplier so as to reduce the circuit scale of a digital filter which uses a large number of multipliers. Outputs of a Booth decoder 4 are stored in registers 5.sub.1 -5.sub.(n+1)/2 provided corresponding to partial product generating circuits 106.sub.1 -106.sub.(n+1)2. By providing control signals from the registers 5.sub.1 -5.sub.(n+1)/2 to the partial product generating circuits 106.sub.1 -106.sub.(n+1)/2, the Booth decoder 4 is made common. The number of Booth decoders which have conventionally been provided in a one-to-one correspondence with the partial product generating circuits can be reduced to one and the multiplier can be simplified.

Abstract: There is disclosed an A-D converter testing circuit wherein exclusive-OR gates (13a, 13b) provide the exclusive-OR of the high-order bits (D.sub.1a, D.sub.1b) of the outputs of A-D converters (12a, 12b) and the exclusive-OR of the high-order bits (D.sub.1b, D.sub.1c) of the outputs of A-D converters (12b, 12c), respectively, and an OR gate (13c) provides the logical sum of the outputs of the both gates, which is "L" if all of the bits (D.sub.1a, D.sub.1b, D.sub.1c) are equal. A tri-state buffer (15a) receives the output of the OR gate (13c) at its control end and receives the bit (D.sub.1c) at its input. When all of the A-D converters are normal, all of the bits (D.sub.1a, D.sub.1b, D.sub.1c) are equal and are applied to the output of the tri-state buffer (15a). When one or some of the A-D converters are abnormal, the output of the tri-state buffer (15a) enters a high-impedance state. The A-D converter testing circuit, therefore, rapidly judges whether the A-D converters are defective or non-defective.

Abstract: Disclosed is an absolute value comparator for comparing respective absolute values of sequentially applied two data. A decoder circuit sequentially converts the applied data into a plurality of bit signals in accordance with a predetermined rule. After a preceding conversion bit signal is once held in a register circuit, the held bit signal is inverted for each bit by an inversion circuit. Thus, a logic circuit receives a preceding inverted bit signal and a succeeding conversion bit signal and outputs an output signal B indicating the result of comparison. Since a full adder is unnecessary, a comparison between the absolute values of the applied data can be made at a high speed.

Abstract: A decode circuit decodes digital signals X1 and X0 as multiplicand to output decoded signals A0-A3. One of these decoded signals A3-A0 is set to be logic 1 in accordance with a value of a multiplicand. A logical operation circuit includes a plurality of operation circuits. Each logical operation circuit performs an independent operation for obtaining a logical value of each bit of the digital signal which is a multiplication result, based on the decoded signals A0-A3 and the digital signals R1 and R0 as a multiplier. Therefore, a result of an operation of a certain bit does not affect results of operations of other bits, so that the logical operation of each bit can be conducted without waiting termination of the logical operations of other bits, which enables high-speed multiplications.

Abstract: A binary data converter is adapted to convert a positive binary data into a negative binary data represented by a complement on two and vice verse. The conversion is effected as follows. A least significant bit of an inputted binary data is outputted as the least significant bit of the converted binary date as it is. With respect to bit signal other than the least significant bit, respective input bit signals less significant than the corresponding input bit signal are ORed. Depending on the result thereof, inverted or non-inverted signals of the corresponding input bit signals are outputted as the bit signals of the converted binary data. Therefore, carry delay is not generated, and thus the operation speed can be increased. Further, the simple circuit structures can reduce the number of required elements.

Abstract: A multiplication processing circuit requiring no digital-analog converter includes a circuit for multiplying a digital multiplication coefficient by a digital multiplicand and outputting the result of multiplication as an analog current signal. The multiplication processing circuit includes a circuit for decoding the digital multiplication coefficient to generate one or a plurality of control signals, a circuit responsive to the digital multiplicand and to the generated control signal for generating a signal indicating, in decimal notation, the result of multiplication of the digital multiplication coefficient by the digital multiplicand, and a circuit for converting the signal indicating the result of multiplication into an analog current signal of a corresponding magnitude. Each of the control signals indicates at least one digital multiplication coefficient in decimal notation.

Abstract: An input analogue signal is converted to a two-valued signal and then it is supplied to each encoder. Each gate signal forming circuit forms a gate signal based on an input digital signal. Each encoder encodes the above stated two-valued signal, an encoding function thereof being determined based on the above stated gate signal. As a result, each encoder outputs a result of multiplication of the two-valued signal and the digital signal in the form of a binary digital signal.

Abstract: First and second comparator groups compare first and second analogue signals applied thereto, respectively, with reference voltages and convert the results of the comparison to binary signals to output the binary signals to an encoding circuit. The encoding circuit converts the binary signals supplied from the first and second comparator groups to digital data of a binary code corresponding to the product of the first and second analogue signals to output the digital data.

Abstract: A semiconductor integrated circuit which is comprised of the following; a plurality of comparators which respectively compare analog values inputted for multiplication with individual reference voltages respectively, multiplication means which controls values outputted from those plural comparators by applying signals corresponding to digital values inputted for multiplication and outputs the product of the values outputted from those plural comparators and the digital values, and a complement operation circuit which converts the value outputted from multiplication means into complement when the digital value is negative.

Abstract: An A/D converter of a serial-parallel comparison type has both multiplying functions of an analog input data and a digital input data. The analog input data V.sub.X is converted into a digital code I.sub.c corresponding to two more significant digits, by a first parallel comparing portion and a first determining circuit, and converted into a digital code I.sub.f corresponding to two less significant digits by a second parallel comparing portion and a second determining circuit. The digital codes I.sub.c and I.sub.f are alternately applied to a control circuit by a first selector circuit. Two more significant bits R.sub.c and two less significant bits R.sub.f of a 4-bit digital input data are respectively applied to a control signal generating circuit by a second selector circuit. Multiplications of R.sub.c I.sub.c, RfIc, R.sub.c I.sub.f and R.sub.f I.sub.f are serially performed within the time period of one conversion by the control signal generating circuit and the control circuit.

Abstract: A semiconductor integrated circuit so arranged that selection is made out of output signals of a decision circuit which determines the levels of analog values inputted as an object for multiplication and multiplication is carried out with respect to the selected signal and the digital value inputted as an object for multiplication, the result of the multiplication being added with the digital value as shifted to the higher position of specified bits, a multiplication result being thereby calculated with respect to the analog value and the digital value, whereby the required area of wiring connections is reasonably reduced and faster operation is assured.

Abstract: A semiconductor integrated circuit includes a plurality of comparators for comparing an analog input with reference voltage or voltages, holding means for holding a digital value, and control means for controlling the outputs of the plurality of comparators by a control signal responsive to the digital value to output the multiplication result of the output values of the plurality of comparators and the digital value. Thus, the integrated circuit can construct a circuit having functions of an A/D converter and a multiplier on one chip.