Abstract: The present invention includes a memory cell area that includes a plurality of transistors, and a core area that is arranged adjacent to the memory cell area. The memory cell area and the core area include a semiconductor layer, and an n-type well region and a first p-type well region formed above the semiconductor layer. The memory cell area further includes a second p-type well region formed under the n-type well region and the first p-type well region in the semiconductor layer. The second p-type well region contacts to at least the first p-type well region.

Abstract: An SRAM cell includes a semiconductor substrate; a first transistor formed in a main plane of the semiconductor substrate; a second transistor formed in the main plane of the semiconductor substrate; and a first wiring layer connecting a gate electrode of the first transistor with a diffusion region of the second transistor inside a first hole and formed to be spaced from the main plane of the semiconductor substrate inside the first hole.