Patents by Inventor Sumito OUCHI

Sumito OUCHI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12490486
    Abstract: A compound semiconductor substrate and a method for manufacturing the compound semiconductor substrate including the steps of forming an electronic traveling layer consisting of a first nitride semiconductor, forming a barrier layer consisting of a second nitride semiconductor with a wider band gap than a band gap of the first nitride semiconductor on the electronic traveling layer, and forming a cap layer with an organometallic vapor phase epitaxy on the barrier layer and in contact with the barrier layer. The cap layer has a C concentration of 5*1017 atoms/cm3 or more and 1*1020 atoms/cm3 or less, and consists of a nitride semiconductor. During the step forming the cap layer, source gas of the nitride semiconductor forming the cap layer and hydrocarbon gas are introduced to a top surface of the barrier layer.
    Type: Grant
    Filed: July 13, 2021
    Date of Patent: December 2, 2025
    Assignee: Air Water Inc.
    Inventors: Sumito Ouchi, Keisuke Kawamura
  • Patent number: 12230679
    Abstract: A compound semiconductor substrate has a Si (silicon) substrate, a first Al nitride semiconductor layer which is a graded layer formed on the Si substrate and whose Al concentration decreases as the distance from the Si substrate increases along the thickness direction, a GaN (gallium nitride) layer formed on the first Al nitride semiconductor layer and having a lower average Al concentration than the average Al concentration of the first Al nitride semiconductor layer, and a second Al nitride semiconductor layer formed on the GaN layer and having a higher average Al concentration than the average Al concentration of the GaN layer. The threading dislocation density at any position in the thickness direction within the second Al nitride semiconductor layer is lower than the threading dislocation density at any position in the thickness direction within the first Al nitride semiconductor layer.
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: February 18, 2025
    Assignee: Air Water Inc.
    Inventors: Sumito Ouchi, Hiroki Sukuki, Mitsuhisa Narukawa, Keisuke Kawamura
  • Publication number: 20230343865
    Abstract: A compound semiconductor substrate and a compound semiconductor device with high quality is provided. The compound semiconductor substrate includes a Si substrate with O concentration of 3*1017/cm3 or more and 3*1018/cm3 or less, a SiC layer formed on the Si substrate, a first nitride semiconductor layer made of AlxGa1-xN (0.1?x?1), formed on the SiC layer and including an insulating or semi-insulating layer, a second nitride semiconductor layer formed on the first nitride semiconductor layer and containing a C-GaNlayer, and an electronic traveling layer formed on the second nitride semiconductor layer and comprising of AlzGa1-zN (0?z<0.1). The sum total thickness of the first nitride semiconductor layer, the second nitride semiconductor layer and the electronic traveling layer is 6 micrometers or more and 10 micrometers or less.
    Type: Application
    Filed: August 19, 2021
    Publication date: October 26, 2023
    Inventors: Keisuke KAWAMURA, Sumito OUCHI, Shigeomi HISHIKI
  • Publication number: 20230215922
    Abstract: A compound semiconductor substrate and a method for manufacturing the same are provided to suppress surface roughness of a barrier layer while suppressing gate leak. A method for manufacturing of a compound semiconductor substrate comprises a step forming an electronic traveling layer consisting of a first nitride semiconductor, a step forming a barrier layer consisting of a second nitride semiconductor with a wider band gap than a band gap of the first nitride semiconductor on the electronic traveling layer, and a step forming a cap layer with an organometallic vapor phase epitaxy on the barrier layer and in contact with the barrier layer. The cap layer has a C concentration of 5*1017 atoms/cm3 or more and 1*1020 atoms/cm3 or less, and consists of a nitride semiconductor. During the step forming the cap layer, source gas of the nitride semiconductor forming the cap layer and hydrocarbon gas are introduced to a top surface of the barrier layer.
    Type: Application
    Filed: July 13, 2021
    Publication date: July 6, 2023
    Inventors: Sumito OUCHI, Keisuke KAWAMURA
  • Patent number: 11476115
    Abstract: A method for manufacturing a compound semiconductor substrate comprises: a step to form an SiC (silicon carbide) layer on a Si (silicon) substrate, a step to form a LT (Low Temperature)-AlN (aluminum nitride) layer with a thickness of 12 nanometers or more and 100 nanometers or less on the SiC layer at 700 degrees Celsius or more and 1000 degrees Celsius or less, a step to form a HT (High Temperature)-AlN layer on the LT-AlN layer at a temperature higher than the temperature at which the LT-AlN layer was formed, a step to form an Al (aluminum) nitride semiconductor layer on the HT-AlN layer, a step to form a GaN (gallium nitride) layer on the Al nitride semiconductor layer, and a step to form an Al nitride semiconductor layer on the GaN layer.
    Type: Grant
    Filed: November 10, 2017
    Date of Patent: October 18, 2022
    Assignee: Air Water Inc.
    Inventors: Mitsuhisa Narukawa, Hiroki Suzuki, Sumito Ouchi
  • Patent number: 11316018
    Abstract: A compound semiconductor substrate includes a SiC (silicon carbide) layer, a AlN (aluminum nitride) buffer layer formed on the SiC layer, an Al (aluminum) nitride semiconductor layer formed on the AlN buffer layer, a composite layer formed on the Al nitride semiconductor layer, a GaN (gallium nitride) layer as an electron transition layer formed on the composite layer, and an Al nitride semiconductor layer as a barrier layer formed on the GaN layer. The composite layer includes C—GaN layers stacked in a vertical direction, and an AlN layer formed between the C—GaN layers.
    Type: Grant
    Filed: March 7, 2018
    Date of Patent: April 26, 2022
    Assignee: Air Water Inc.
    Inventors: Mitsuhisa Narukawa, Sumito Ouchi, Hiroki Suzuki, Keisuke Kawamura
  • Publication number: 20220077288
    Abstract: A compound semiconductor substrate has a Si (silicon) substrate, a first Al nitride semiconductor layer which is a graded layer formed on the Si substrate and whose Al concentration decreases as the distance from the Si substrate increases along the thickness direction, a GaN (gallium nitride) layer formed on the first Al nitride semiconductor layer and having a lower average Al concentration than the average Al concentration of the first Al nitride semiconductor layer, and a second Al nitride semiconductor layer formed on the GaN layer and having a higher average Al concentration than the average Al concentration of the GaN layer. The threading dislocation density at any position in the thickness direction within the second Al nitride semiconductor layer is lower than the threading dislocation density at any position in the thickness direction within the first Al nitride semiconductor layer.
    Type: Application
    Filed: December 10, 2019
    Publication date: March 10, 2022
    Inventors: Sumito OUCHI, Hiroki SUKUKI, Mitsuhisa NARUKAWA, Keisuke KAWAMURA
  • Publication number: 20220069090
    Abstract: A compound semiconductor substrate that can improve in-plane uniformity of current-voltage characteristics in the vertical direction is provided. A compound semiconductor substrate includes a center and an edge which is 71.2 millimeters away from the center when viewed in a plane. When a film thickness of the GaN layer at the center of the compound semiconductor substrate is W1 and a film thickness of the CaN layer at the edge is W2, film thickness error ?W represented by ?W (%)=W1?W2|*100/W1 is greater than 0 and 8% or less. The average carbon concentration in the depth direction at a center of the CaN layer is 3*1018 pieces/cm3 or more and 5*1020 pieces/cm3 or less. When a carbon concentration at a center position of the depth direction at the center of the GaN layer is concentration C1 and a carbon concentration at a center position of the depth direction at the edge of the GaN layer is concentration C2, concentration error ?C represented by ?C (%)=|C1?C2*100/C1 is 0 or more and 50% or less.
    Type: Application
    Filed: January 8, 2020
    Publication date: March 3, 2022
    Inventors: Hiroki SUZUKI, Sumito OUCHI, Mitsuhisa NARUKAWA, Keisuke KAWAMURA
  • Publication number: 20200402922
    Abstract: A compound semiconductor substrate in which the warpage can easily be controlled is provided. The compound semiconductor substrate comprises a SiC (silicon carbide) layer, an AlN (aluminum nitride) buffer layer formed on the SiC layer, and a lower composite layer formed on the AlN buffer layer, and an upper composite layer formed on the lower composite layer. The lower composite layer includes a plurality of lower Al (aluminum) nitride semiconductor layers vertically stacked and a lower GaN (gallium nitride) layer formed between the plurality of lower Al nitride semiconductor layers. The upper composite layer includes a plurality of upper GaN layers stacked vertically and an Al nitride semiconductor layer formed between the plurality of upper GaN layers.
    Type: Application
    Filed: December 6, 2018
    Publication date: December 24, 2020
    Inventors: Sumito OUCHI, Hiroki SUZUKI, Mitsuhisa NARUKAWA, Keisuke KAWAMURA
  • Publication number: 20200020778
    Abstract: A compound semiconductor substrate includes a SiC (silicon carbide) layer, a AlN (aluminum nitride) buffer layer formed on the SiC layer, an Al (aluminum) nitride semiconductor layer formed on the AlN buffer layer, a composite layer formed on the Al nitride semiconductor layer, a GaN (gallium nitride) layer as an electron transition layer formed on the composite layer, and an Al nitride semiconductor layer as a barrier layer formed on the GaN layer. The composite layer includes C—GaN layers stacked in a vertical direction, and an AlN layer formed between the C—GaN layers.
    Type: Application
    Filed: March 7, 2018
    Publication date: January 16, 2020
    Inventors: Mitsuhisa Narukawa, Sumito OUCHI, Hiroki Suzuki, Keisuke Kawamura
  • Publication number: 20190279864
    Abstract: A method for manufacturing a compound semiconductor substrate comprises: a step to form an SiC (silicon carbide) layer on a Si (silicon) substrate, a step to form a LT (Low Temperature)-AlN (aluminum nitride) layer with a thickness of 12 nanometers or more and 100 nanometers or less on the SiC layer at 700 degrees Celsius or more and 1000 degrees Celsius or less, a step to form a HT (High Temperature)-AlN layer on the LT-AlN layer at a temperature higher than the temperature at which the LT-AlN layer was formed, a step to form an Al (aluminum) nitride semiconductor layer on the HT-AlN layer, a step to form a GaN (gallium nitride) layer on the Al nitride semiconductor layer, and a step to form an Al nitride semiconductor layer on the GaN layer.
    Type: Application
    Filed: November 10, 2017
    Publication date: September 12, 2019
    Inventors: Mitsuhisa Narukawa, Hiroki Suzuki, Sumito Ouchi
  • Patent number: 10186585
    Abstract: A semiconductor device which can reduce power consumption and a method for manufacturing the same are provided. A semiconductor device comprises an Si (silicon) substrate, an SiC (silicon carbide) layer formed on the surface of the Si substrate, an AlN (aluminum nitride) layer formed on the surface of the SiC layer, an n-type GaN (gallium nitride) layer formed on the surface of the AlN layer, a first electrode formed at the surface side of the GaN layer, and a second electrode formed at the reverse face side of the Si substrate 1. The magnitude of electrical current which flows between the first electrode and the second electrode depends on electrical voltage between the first electrode and the second electrode.
    Type: Grant
    Filed: August 12, 2015
    Date of Patent: January 22, 2019
    Assignee: Air Water Inc.
    Inventors: Akira Fukazawa, Sumito Ouchi
  • Publication number: 20170236907
    Abstract: A semiconductor device which can reduce power consumption and a method for manufacturing the same are provided. A semiconductor device comprises an Si (silicon) substrate, an SIC (silicon carbide) layer formed on the surface of the Si substrate, an AIN (aluminum nitride) layer formed on the surface of the SiC layer, an n-type GaN (gallium nitride) layer formed on the surface of the AIN layer, a first electrode formed at the surface side of the GaN layer, and a second electrode formed at the reverse face side of the Si substrate 1. The magnitude of electrical current which flows between the first electrode and the second electrode depends on electrical voltage between the first electrode and the second electrode.
    Type: Application
    Filed: August 12, 2015
    Publication date: August 17, 2017
    Inventors: Akira FUKAZAWA, Sumito OUCHI